Test2

152. Which MIPS registers should not be used by the programmer?

$at

149. Which register is used in allocation of memory on the heap? (104)

$gp (global pointer)

112. In a 32-bit MIPS instruction, the location of bit 0 (the least significant bit)

(74) is the farthest right bit

166. The 16-bit immediate field of a conditional branch instruction can jump through what address range?

+-128K bytes +-32K instructions

237. Ignoring the sign bit, the length of the product of an m-bit multiplicand and an n-bit multiplier is (183)

A. up to m + n bits C. The sum of the lengths of the shortest expression of the operands.

249. A simple and efficient way to implement division is to (189)

A. use hardware to perform "grammar school" division B. Implement long division in hardware.

242. Signed multiplication (187)

B. XORs the sign bits to determine the sign of the result. D. forms the product from unsigned numbers and two-complements the product if the multiplicand and multiplier signs are different

234. After an exception, the EPC register contains (182)

B. the PC when the exception occurred. F. The address of the instruction where processing may resume.

202. Intel's instruction set is characterized by

Backwards compatibility

136. A sequence of instructions without branches in the middle is call a(n) (93)

Basic block/basic code block

236. Twos-complement is a method of (182)

D. Converting a number such that its sum with the original number is zero. F. Expressing negative numbers

262. The standard for floating point notation is (198)

D. IEEE-754

215. The reason the "ugly" Intel architecture has survived over the years is that (157)

D. It was adopted for the IBM PC in the early 1980s. G. It has huge market forces behind it.

147. In a recursive procedure (101)

D. Local storage must be allocated on the stack.

201. In general, a more complex instruction set means

D. More compact code and lower instruction count

259. A floating point number is composed of (197)

D. One bit for the sign, 8 for the exponent and 23 for the fraction. G. Sign, Exponent, Fraction

139. A good argument for MIPS not having a hardware instruction for "branch on less than" is: (94)

D. The complexity of the instruction would stretch the clock cycle for many more, less complicated instructions. F. It can be produced from two simple instructions

248. The two operands of the division process are (189)

D. The dividend and the divisor G. Can be stored in conventional registers.

105. What is the reason that addresses of integer data stored in main memory must have the last two bits set to 0? (69)

D. There is an alignment restriction E. Word data must be four-byte aligned

204. When floating point operations were introduced in the Intel processor line, (150)

D. They were not performed in the CPU itself. G. They were performed in a separate off-chip processor.

144. To adjust the stack pointer to make room for three 32-bit values, the correct instruction is (99)

D. addi $sp, $sp, 0xfff4 E. addi $sp, $sp, -12

110. Immediate operands are (72)

Data located in the instruction

193. Which operation is unsupported in the ARM-7 instruction set?

Divide/div

225. In binary, 1011 - 100 = (179)

E. 111 G. 0x7

177. Dynamically Linked Libraries (DLLs)

Are not linked until runtime and use "lazy linking"

188. Two methods of indexing lists of numbers are

Arrays and pointers

101. For a given method, which language will have the most lines of code? (66)

Assembly

122. Which is not a MIPS type of instruction? (82)

B type

161. Which is not a type of MIPS instruction?

B-S types

267. which number below is the hex representation of a negative floating point number? (202)

B. 0x80100000 E. 0xC0100000

224. In binary, 1011 + 1 = (179)

B. 1100 E. 0xC

232. In multimedia arithmetic, an overflow often results in (181)

B. Achieving a maximum value, but no greater. D. saturation

185. What is the fastest way of saving a variable in the $a0 register

B. Add it to $0 and store it in another register. Copy it to another register

246. An invalid mathematical operation which can happen when computers do calculations is (189)

B. Arithmetic overflow. D. Division by zero

240. Multiplying two 32 bit numbers (184)

B. Can result in a 64-bit product

104. What is the generic name of instructions which move data between the processor and memory? (68)

B. Data transfer instructions, Data transfer

253. In determining the sign of the quotient, what rule must always hold? (193)

B. Dividend = Quotient * Divisor + Remainder G. Remainder = Dividend - Quotient * Divisor

244. How is multiply overflow handled in MIPS? (188)

B. It will not occur if a 64-bit result is used D. Software must check the hi half of the product

219. Which is not a MIPS design principle? (161)

B. Speed = Efficiency.

199. In the ARM 12-bit immediate field, the eight least significant bits are zero-extended to a 32-bit value, then rotated right the number of bits specified in the first four bits of the field multiplied by two. This allows

B. The most frequently used 32-bit values to be represented. All powers of 2 in a 32-bit value to be represented.

256. One way of making the division process faster is to (194)

E. Looking up partial results in a table rather than use combinational logic to obtain the G. Guess intermediate results and make changes if the guesses are wrong.

99. The C code "d = a - e" could be represented in MIPS assembly as (65)

E. SUB d, a, e AND F. sub $t0, $t1, $t2 where d=$t0, a=$t1 and e=$t2

245. Faster multipliers (188)

F. Are easier to implement than faster dividers. G. Perform more than one operation at once

182. What kind of sort involves successive exchanges of values in an array until they are in order? (135)

F. Bubble sort

206. With the arrival of multimedia applications in the late 1990s, Intel introduced (150)

F. Instructions which could operate on multiple data at once. G. Single Instruction Multiple Data (SIMD) instructions.

186. Inlining saves

F. The overhead of a procedure call, Execution time at the expense of code size.

203. Intel's 1978 microprocessor, the 8086 had a 16-bit architecture with

F. sixteen-bit registers, some of which were special-purpose G. Fewer registers than are common now.

187. Machine Code optimized for speed has the fewest instructions

False

211. Registers in the current Intel processors are the same length (153)

False

218. The 64-bit ARM v8 is an extension of the design of the 32-bit ARM v7. (159)

False

221. Computers write numbers to memory differently than characters (178)

False

223. Because binary representation involves only 0's and 1's, carrying in addition is unnecessary. (179)

False

226. In a 32-bit register, overflow can occur when adding a positive and negative number (179)

False

264. Negative exponents in floating point binary are represented as twos-complement numbers (200)

False

257. Binary representations of floating point numbers have greater range but less precision than binary representations of integers (196)

True

94. Execution time is the only valid measure of performance (52)

True

156. To move a unicode character from memory to a register, which MIPS instruction should be used?

lhu

153. The MIPS instruction(s) used to load a 32-bit register with data which is hard-coded into the program is/are

lui, ori

159. Loading a 32-bit value from immediate data into a MIPS register can be done with which instructions

lui, ori

138. Register $t0 contains 0xFFFFFFFF and register $t1 contains 0x00000000. Which instruction will see $t0 as greater than $t1? (94)

sltu $s0, $t0, $t1

184. If one subroutine calls another, we must at least preserve

the $ra (return address) register

140. Which signed byte has the smallest value? (95)

0x80 and 0x81

126. How many bits in a MIPS instruction are allocated for immediate data (84)

16

109. The typical MIPS immediate instruction (e.g., ADDI, SUBI) contains references to how many registers? (72)

2

131. How many Branch instructions does the MIPS processor recognize? (90)

2

133. MIPS conditional branch instructions require the comparison of (90)

2 registers, rs rt

261. In single-precision binary floating point notation, the fraction is ______ bits long (198)

23

209. Intel's widest register is ____ bits wide (152)

256/2^8

163. The J instruction immediate field is _____ bits.

26

162. The J-type instruction has an immediate field which is ____ bits long

26, 26 unsigned

108. The typical MIPS register-to-register arithmetic instruction (e.g., ADD, SUB) contains references to how many registers? (72)

3

265. The length of a single-precision floating point binary number is ____ bits (200)

32

125. To refer to each of the 32 MIPS processor registers, an instruction needs (83)

5

266. The length of a double-precision floating point binary number is ____ bits (200)

64

260. In single-precision binary floating point notation, the exponent is ______ bits long (198)

8

114. In binary, subtracting a large positive number from a small positive number produces (75)

A 1 in the left bit of the result

168. The branch instructions can jump plus or minus 32k instructions. What if we need to branch farther than that?

A jr instruction can be used if the target is fixed, Branch logic can be combine with the jump instruction to do a longer branch.

107. If four-byte alignment is required, at which address could an integer not be stored? (70)

A. 0x0041000E , 0x00410003

111. Which 16-bit hex value would represent a negative number? (74)

A. 0x8001 , 0xffff

228. In binary, 1111...10001 - 1111...11000 = (180)

A. 0xfffffff9 C. 1111...11001

198. Each ARM instruction begins with _____

A. A four-bit code which determines whether the instruction will execute and Condition codes

210. In general, Intel's arithmetic instructions (152)

A. A source and destination register be the same.

230. In which situation does an overflow occur? (180)

A. Adding two positive numbers and getting a negative result.

212. An addressing scheme where the address is a base register plus 2^n times an index (where n is specified in 2 or 3 bits of the instruction) is called (154)

A. Base plus scaled index. G. Scaled.

207. A large number (more than 200) instructions were added to the intel instruction set (150)

A. Between 1999 and 2001 for floating point and multimedia purposes E. Because of the demand for audio and video processing

151. When a program is loaded into memory, the text segment

A. Contains the MIPS machine code

263. the NaN notion can result from (199)

A. Divide by zero B. Performing an operation with a NaN value.

205. Intel's first 32-bit processor, the 80386 appeared the same year as the MIPS and ARM processors. However (150)

A. Intel continued to build on their former instruction set. F. Intel already had a huge user base while ARM and MIPS had virtually none.

118. The problem with one's-complement representation of negative numbers was (79)

A. It was more difficult to implement than twos-complement. There were two zeroes

100. Which language will have the most lines of code to implement a sort algorithm? (66)

A. MIPS Assembly Language, assembly code

120. What is the native, binary form of instructions used by the processor? (81)

A. Machine instructions and language

243. Moore's law allows multiplications to be faster because (187)

A. More transistors means more adders, up to one per multiplier bit G. More hardware means operations can be done in parallel.

233. The EPC register is used for (182)

A. Storing the address of the instruction causing overflow B. Storing the PC when an exception occurs.

227. Which does not indicate an overflow? (179)

A. Subtracting two negative numbers and getting a positive result. G. Subtracting one positive number from another and getting a negative result.

106. Memory alignment means (69)

A. The bottom two bits of a MIPS instruction address must be zero G. 4-byte words must begin on 4-byte boundaries

247. The two parts of the integer division result are (189)

A. The quotient and the remainder D. Stored in the HI and LO registers.

255. If by mistake you divide a positive number by a negative number using unsigned divide (divu) (194)

A. The remainder is the dividend. F. The quotient is zero.

192. Which is not a difference between the MIPS and ARM processor (146)

A. The year of first product announcement, Use of RISC instructions.

251. Signed division can be done by (192)

A. XORing the sign bits of the operands and calculating the signs of the remainders. E. Doing unsigned division and setting the signs of the quotient and remainder based on signs of the operands

235. Addition can be speeded up by (182)

A. anticipating the high-order carry bit E. Performing add operations in parallel with more hardware.

189. Which is the fastest way to convert an array index to a memory address location

A. shift left 2 in hardware. Reroute address lines, each to the second one to its left.

183. Which of the following is a pseudoinstruction?

Move, blt

208. In the 1970s, a company named Zilog produced a better chip than Intel, but used intel's architecture. More recently, what company has been doing this? (151)

AMD

214. Which processor uses instructions which are of different lengths (155)

AMD and Intel

155. The difference between ASCII and Unicode is

ASCII represents up to 256 characters, and Unicode represents up to 65536 characters. Unicode can represent more characters than ASCII.

115. Which set of binary numbers are the two's complement of each other? (76)

C. 00000001 11111111 AND 0101 1011

119. In twos complement notation, the most negative value is (79)

C. 0x8000

116. Which signed number is the same as 0x80? (78)

C. 0xff80 F. 0xFFFFFF80

222. Twos complement is (179)

C. A way of representing negative numbers F. A way of changing the sign of a number.

191. The most popular instruction set for embedded devices is the _____ ISA

C. Acorn RISC Machine

239. The most common use of processor arithmetic is for (184)

C. Address calculations. and Determining locations in memory.

103. In MIPS, data is moved to and from memory using (68)

C. Data transfer instructions. Load and Store instructions

197. The ARM processor uses a status word of four bits: negative, zero, carry and overflow. What is this status word used for?

C. Deciding whether or not to execute the instruction. Conditionally executing instructions.

217. Early microprocessors which disappeared from the market did so because (158)

C. Insufficient address bits E. They couldn't handle expanding memory demands.

254. Using many adders to speed up division (194)

C. Is limited in its effectiveness because there are branches in the logic. G. Won't work because decisions have to be made after the subtractions.

121. All MIPS instructions have (81)

C. Length of 32 bits, An Operations Code field

231. Processing data for multimedia, especially graphics, has led to (181)

C. Long registers with carry partitions. G. register partitioning for vector math

258. Normalized scientific notation (196)

C. Means the number left of the point is not zero. E. In binary means that there is only a 1 to the left of the binary point.

195. The MIPS and ARM instruction sets differ widely on how they perform

C. Memory addressing. Compares and conditional branches

145. If subroutine A calls subroutine B (100)

C. Subroutine A must preserve $ra. G. Subroutine A is a non-leaf subroutine.

252. The sign of an integer divide is (192)

C. The XOR of the dividend and divisor signs.

148. What MIPS registers bound the local variable storage area for a subroutine? (103)

C. The stack pointer and the frame pointer. G. $fp and $sp

143. The jal instruction is unique because it also (97)

C. Writes to the $ra register (copies $pc to $ra)

238. A simple implementation of a multiplier (183)

C. shifts the multiplicand left for each bit of the multiplier, and adds it to the product if the multiplier bit is 1 F. Performs a binary version of elementary school-style multiplication.

216. The market in which Intel processors do not do well is (158)

Cell phones/PMD

172. In the traditional scheme of compiling and running a program, what is the sequence of actions?

Compile, assemble, link, load.

174. Which describes a symbol table?

D. A table that matches names of labels to the addresses of the memory words that instructions occupy. A list of needed and supplied program locations.

250. Whereas a simple multiplication algorithm is based on read a bit, conditionally add and shift, a simple division is based on (190)

D. Checking to see if the result of a subtraction is positive, and setting a bit if so. F. Subtract and shift and conditionally write a bit

190. While the C language is compiled and linked, the Java language is __________

D. Compiled and Interpreted, Run with the JVM

124. The easiest conversion is from (82)

Hex to bin, bin to hex

160. A branch instruction is a(n) ____ instruction

I-type

117. The interface between low-level hardware and software is called (78)

Instruction set architecture

95. What is the vocabulary of commands understood by the processor? (62)

Instructions and instruction set

96. The vocabulary of the CPU is the (62)

Instructions and instruction set

229. When MIPS detects an overflow condition a(n) _____ occurs (180)

Interrupt and exception

164. How is immediate data handled in branch instructions

It is shifted left 2 after being sign extended and added to the program counter, is sign extended, shifted left 2 and added to the program counter

170. The MIPS instruction set does not include a "branch on less than". Why not? (120)

It would take too long as a single instruction and stretch the clock cycle for all other instructions, It can be done by a combination of simple instructions.

134. The Program Counter contains the address of the next instruction to be executed. Which MIPS instruction would affect the value of the PC? (90)

J, BEQ/BNE

178. What is the output of a Java compiler

Java byte code, a class file

179. What is the input to the Java Virtual Machine

Java byte code, class file

157. Some character sets use 16-bit characters. The would be loaded by which MIPS command?

LHU

158. Unicode consists of 2-byte characters. Which MIPS instruction should be used to load a unicode character

LHU

176. Which is not an advantage to using compiled libraries of commonly used code (e.g., a math library)?

Makes the executable run faster

98. The contents of a memory location whose address is contained in register $s1 may be expressed as: (64)

Mem[Regs[$s1]]

150. A disadvantage of recursion is that it can consume a lot of (104)

Memory on the stack, stack space

180. In a Just-in-Time compiler, a code analyzer identifies the "hot" methods. What is a "hot" method?

Methods which are called frequently

154. Storage and use of decimal numbers for computation in computers is

More difficult to implement and consumes more memory than needed. Sometimes useful in financial applications.

196. How many extra instructions does the ARM instruction set require to conditionally skip a single instruction?

None/zero

132. The BEQ and BNE instructions are (90)

Not/conditional jumps

123. Which instruction field is 6-bits long? (82)

Op and Function code

102. In the instruction "add $s0, $s1, $s2", $s1 and $s2 are (67)

Operands, registers

165. An addressing scheme where the target address is the sum of the program counter and a number specified in an instruction is

PC-relative addressing G. Program Counter relative addressing

129. Which is not a field in the MIPS instruction format? (88)

Precision, instruction length00

173. An assembly instruction which is not executed in hardware but rather decomposed into a more verbose assembly-language construct by the assembler is called a

Pseudoinstruction

97. The fastest access to data is via (64)

Registers

169. The MIPS J instruction uses ______ addressing

Replace bottom 28 bits of PC, Pseudodirect

171. What best describes what a linker does?

Resolves references among separate code modules. Combines separately compiled code and data modules into a single executable file.

128. The shamt field in the MIPS instruction is use for which instruction? (88)

SLL, SRL

181. What does the following code do? lw $t0, 0($s0) lw $t1, 4($s0) sw $t0, 4($s0) sw $t1, 0($s0)

Sorts lists of numbers

127. Which instruction does the MIPS processor not have? (87)

Subi, not

137. To create all conditions for branches, MIPS uses which set of instructions? (93)

The $0 register, slt/slti and bne/beq

175. What is the output of a linker?

The binary executable/executable

146. Which statement is true? (100)

The stack pointer must be in the same position before and after the call.

113. Negative numbers can be represented in binary (75)

True

194. The MIPS instruction set has many more data addressing modes than the ARM set.

True

200. ARMS processors can load blocks of memory into multiple registers with one instruction

True

213. The Intel instruction set has special instructions for string move and string compare (154)

True

220. Integer addition and subtraction use the same add-and-carry logic in the CPU. (178)

True

241. A 32-bit multiplier can be constructed from a single 64-bit register which can be read and written in different places. (186)

True

130. What operation wound combine 0x80000000 with 0xC0000000 to produce 0x40000000? (89)

XOR

167. The branch offset in a MIPS BEQ or BNE instruction

is the number of instructions forward or back that the branch takes.

142. Which instruction is commonly used for a subroutine call? (96)

jal

141. A jump table in combination with the ____ instruction can be used to implement a case or switch statement. (95)

jr