Unit 5 Cambridge CSP 23-24

Accumulator (if only 1 register is general-purpose)

- A general-purpose register that stores a value before and after the execution of an instruction by the ALU. - Only 1 value stored at a time

Active Components of the CPU

- ALU: responsible for arithmetic or logic processing - CU: 1. controls data flow through processor and rest of computer, 2. ensures program instructions are handled accurately, 3. TWO clocks that are used to synchronized processors. 4. Functions of CU is more diverse

2 Clocks Provided by the CU

-Internal clock controls cycle of activity WITHIN the processor. -System clock controls activity OUTSIDE the processor.

3 distinct components that make up the system bus

1. Address bus 2. Data bus 3. Control bus

USB Standards

1. Can handle 127 devices 2. Devices can be attached while the computer is on and automatically configured to use.

Cache Memory

1. Fastest component of the Immediate Access Store 2. Performance improves with increase storage size and with increase rate of access. 3. Fastest access is obtained with all or part of cache on the CPU chip.

Describe what happens in the decode stage

1. Instruction stored in CIR is received as input by the circuitry within the control unit. 2. Control unit will send signals to appropriate unit so execute stage can begin.

Control Bus

1. It is bidirectional 2. Transmits a signal from the control unit to there system components. 3. Extended width is not required so the controller have only 8 wires. 4. Major use is to carry timing signals at time intervals dictated by the clock cycle to ensure data transmission is synchronized.

Three important things to remember about Registers

1. MDR must act as buffer - transfer of data inside the processor takes place much more quickly than transfers outside the processor. 2. Index register (IX) can be abbreviated as IR but in some sources the current instruction register (CIR) is abbreviated as IR. 3. Abbreviation PC for Program Counter will only be used when register notation is being used other wise the other PC.

High Definition Multimedia Interface (HDMI)

1. Provide a connection to a screen 2. Allows transmission of high-quality video including the audio component.

Bus Width

1. Refers to the number of parallel lines that make up a particular kind of computer bus. 2. Indicates the number of electric wires or bits that build up the data bus. 3. ISA-support 8- and 6- bid widths, EISA and MCA support 16 and 32 bit widths and PCI support 32-64 bit widths.

Video Graphics Display (VGA)

1. Some peripherals require ports different from USB. 2. VGA provides video only 3. If audio is required, a VGA port is not a suitable one.

Plug-and-play

1. The aim of plug-and-play was to remove technical expertise allowing any computer user to connect a peripheral. 2. Plug-and-play was fully realized by the creation of USB. 3. Alternate technology is FireWire which is NOT COMMON.

5 Basic Features of Von Neumann's Model

1. There is a processor. 2. Processor has direct access to memory 3. Memory contains a "stored program" (can be replaced at anytime & data is required. 4. Stored program consists of individual instructions. 5. Processor executes instructions sequentially.

(Extension) Calculate the minimum time period that could separate successive activities on system above:

1.7 Ghz = 1 / (1.7e9) secs as the time between clock signals. Answer = 5.9e-10 secs which is the minimum time period that could separate successive activities (sig figs are wrong).

Very simple computer with ___ bits allows 2^___ or ________ memory locations to be directly as assessed, which is inadequate

16, 2^16 or 65536 memory locations

The last thing to happen in the fetch stage

3. Instruction stored in MDR is transferred within CPU to CIR. a) Clock cycle is controlled by system clock which have settings that allow one data transfer from memory to take place in the time defined for one cycle. b) Counter is incremented by 1, but instruction that had just been loaded might be a jump instruction. In this case, program counter will be updated in accordance with the jump condition. Can only happen after instruction has been decoded.

(Extension) In an advertisement for a laptop, 4GB, 1Tb, 1.7Ghz

4 Gb = memory capacity 1 Tb = hard disk capacity 1.7 Ghz = processor clock speed

Address Bus

A component that carries an address to the memory controller to identify a location in memory which is to be read from or written to. Can be to the I/O system to identify source/destination of the data. One way street Can only be used to send an address to the memory or I/O controller.

Data Bus

A component that carry data to the memory or to an output device or can carry data from the memory or from an input device. Function of data bus is to carry data Data bus is two way Could carry data to and from the CPU Could carry data to and from an I/O device

Bus (not a storage device)

A parallel transmission component with each separate wire carrying a single bit. Mechanism for data to be transferred from one system to another. System bus connects CPU to the memory and to the I/O system.

Word

A small number of bytes that handled as unit by the computer system. Significance: a grouping of the system can handle as one unit. Typical word lengths: 16, 32, 64 bits 2, 4, 8 bytes

External Port

Allows the computer user to connect a peripheral I/O device.

ALU

Arithmetic and Logic Unit

How are data bus width and word length related?

Bus width is important in considering how data bus is used -- same as word length. If not possible, bus width can be 1/2 the word length so the full word can be transmitted in two consecutive data transfers, which affects the performance of the system.

CPU

Central Processing Unit

Status Register

Contains bits that are either set or cleared which can be referenced individually.

CU

Control Unit

Port

Each I/O device is connected to a port.

Controller

Handles the interaction between the CPU and an I/O device

Components directly accessible by the processor are referred to as ____

Immediate Access Store (IAS)

_______ components outside processor as fast as the processor itself.

None

CPU can send/receive data to/from which buses?

Send: Control bus, Address bus, Data bus Receive: Control bus, Data bus

Input and Output can send/receive data to/from which buses?

Send: Control bus, Data bus Receive: Address bus

Memory can send/receive data to/from which buses?

Send: Control bus, Data bus Receive: Control bus, Address bus, Data bus

Index Register (IK)

Stores a value; used only for indexed addressing

Memory Data Register (MDR)

Stores data that has just been read from memory or is just about to be written to.

Memory Address Register (MAR)

Stores the address of a memory location or an I/O component which is about to have a value read from or written to.

Program Counter

Stores the address of where the next instruction is to be read from.

Current Instruction Register (CIR)

Stores the current instruction when it is being decoded & executed.

Registers

The "other" componenets of CPU, and is placed very close to the ALU. The benefit is that it allows very short access time. Storage size consists of 16, 32, 64 bits.

Clock Speed (CPU will often have)

The frequency defines the minimum period of time that separates successive activities

Latest version of USB

USB 3.2 (according to Google, USB 4)

USB

Universal Serial Bus Tip: is a bus A USB drive stores data and is connected to a USB port which allows data to be transmitted along the bus.

During the clock cycle

a) Instruction held in address pointed to by MAR is fetched into the MDR. b) Address stored in the program counter is incremented.

Word length influences system architecture in regards to _______ of components.

capacity usual for register size to match word length

Processor ____ _____ is very important factor governing the processing speed of the system.

clock speed

Memory Address Register

connected to Address Bus

Control Unit

connected to Control Bus

Memory Data Register

connected to Data Bus

Internal Port

if the connected I/O device is an integral part of the computer system.

Processors are much faster than IAS, modern processors are more complex. CPU chip or integrated circuit will be a ____ ____

multi core 1. each core is a separate processor 2. performance improves with increasing number of cores

What defines the shortest possible time that any action can take?

one clock cycle

First Step of Fetch Cycle

the address in the program counter is transferred within the CPU to the MAR.

Address bus' width defines

the number of bits in the address' binary code

Status register - how is each indiv. bit used?

used as a logical flag