Assembly Quiz 6

346. Dynamic pipeline scheduling is done by (339) A. The compiler B. The programmer C. Oil companies. D. The processor

D. The processor

312. The writeback mux appears in stage 5 of the MIPS processor pipeline. What device is the destination of the writeback mux output? (287) A. The ALU B. The branch adder C. Instruction memory D. The register file E. The branch target mux F. Data Memory G. The PC

D. The register file G. The PC

328. Branch predictors should predict that the branch at the end of a loop is rarely taken (321) A. F B. T

A. F

304. Which kind of hazard occurs when two pipeline stages require the same hardware, and the hardware is in use? (278) A. Intentional B. Structural C. Data D. Exception E. Accidental F. Control

B. Structural

297. Doing laundry in four equally long stages allows the process to be sped up by a factor of ____ over repeatedly doing the process end-to-end. (273) A. Eight B. Seven C. 1.75 D. Two E. Four

E. Four

339. What kind of parallelism does pipelining support? (332) A. Request Level Parallelism B. Control level parallelism. C. Data Level Parallelism D. Thread Level Parallelism E. ILP F. Flow parallelism. G. Instruction Level Parallelism

E. ILP G. Instruction Level Parallelism

321. Once a data hazard is detected, the MIPS processor typically resolves it by (310) A. Storing variables on the stack. B. Deasserting all control lines in that stage. C. Loading the program counter. D. Causing the instruction to be No-oped E. Setting the input muxes to the ALU F. Stalling the instruction G. Asserting the Forward A or Forward B lines.

E. Setting the input muxes to the ALU G. Asserting the Forward A or Forward B lines.

301. What determines the clock cycle time of a pipelined, multi-stage instruction? (275) A. Market requirements. B. Total execution time divided by number of stages C. The number of instructions executing at once. D. The duration of the shortest stage E. The stage which takes the longest. F. The duration of the longest stage G. The duration of the first stage

E. The stage which takes the longest. F. The duration of the longest stage

282. When does combinational logic happen? (249) A. Between the rising edges of two adjacent clock pulses B. After the state is sampled and before the state is stored C. Between the falling edges of two adjacent clock pulses D. Between adjacent cycles E. After Instruction Fetch and before Instruction Decode F. During instruction Fetch G. During Data Write

A. Between the rising edges of two adjacent clock pulses B. After the state is sampled and before the state is stored

331. As pipelines become deeper (323) A. Branch instructions have more branch delay slots B. Branch prediction becomes more accurate C. Branch instructions can branch farther D. Exception handling becomes simpler

A. Branch instructions have more branch delay slots

313. In which pipeline stage is the ALU found? (296) A. EX B. IF C. Execute D. ID E. WB F. Control G. Hazard Detetion

A. EX C. Execute

348. Which of the following are not used in dynamic scheduling? (340) A. reorder buffer B. Reservation station C. Commit unit D. Crossbar architecture

D. Crossbar architecture

286. How many five-bit inputs does the Register File have (253) A. Non B. One C. Two D. Five E. Four F. Three

F. Three

296. Instructions which execute in a single clock cycle execute faster than instructions requiring multiple clock cycles (272) A. F B. T

A. F

322. The forwarding unit moves data backwards in the pipeline (312) A. T B. F

B. F

292. In the branch instructions, the number of instructions to skip is given in the immediate field. How long is this field? (262) A. 16 bits B. 17 bits C. 26 bits D. 5 bits E. 15 bits F. 18 bits

A. 16 bits

300. A single-cycle instruction spends 100, 200, 150, 250 and 200 pico seconds in the IF, ID, EX, MEM and WB stages of the processor. If the processor is pipelined, how long should the clock cycle be? (275) A. 250 ps B. 200 ps C. 900 ps D. 300 ps E. 180 ps F. 100 ps

A. 250 ps

284. To add two numbers, you would use what device? (252) A. ALU B. Cache C. Sign-extender D. Arithmetic Logic Unit E. MUX F. Branch control G. Control Unit

A. ALU D. Arithmetic Logic Unit

349. Out of order execution happens when (341) A. All data is available for a subsequent instruction B. The reservation stations are full C. The reorder buffer is empty D. The Supreme Court intervenes

A. All data is available for a subsequent instruction

337. What characterizes imprecise exception handling? (331) A. Allowing some instructions begun after the one causing the exception to complete. B. The exception handling routine does not know what to do. C. Truncation error. D. Roundoff error. E. The inability to associate the cause of the exception with a specific instruction F. Knowing which instruction must be restarted. G. The use of non-pipelined architectures with pipelined instructions

A. Allowing some instructions begun after the one causing the exception to complete. E. The inability to associate the cause of the exception with a specific instruction

289. The ALU zero output is used in handling which instruction? (256) A. BNE B. JAL C. SLT D. ADD

A. BNE

288. What happens to the 16-bit sign-extended offset of a branch instruction before it is added to the program counter contents? (256) A. It is shifted left two bits B. It is shifted right two bits C. It depends on the result of the compare D. it is set to zero E. it is added to the program counter. F. It replaces the program counter.

A. It is shifted left two bits

279. The Arithmetic Logic Unit is not used for which set of instructions (246) A. Jump (J) B. J-types C. Load (LW, LH, LB) D. Branch (BEQ, BNE) E. Store (SW, SH, SB) F. I-types G. R-types

A. Jump (J) B. J-types

345. Using memory offsets in load and store instructions, multiple registers for sequential loads and significantly reducing the number of end-of-loop branch instructions characterizes (338) A. Loop unrolling B. Issuing multiple instruction per clock C. Compiling the code backwards D. Having more registers available

A. Loop unrolling

342. To be effective, multiple issue typically requires (336) A. More hardware. B. Larger main memory C. Programmer awareness. D. Larger heat sinks.

A. More hardware.

310. Guessing which branch to take is an acceptable way of resolving control hazards (284) A. T B. F

A. T

319. It is possible that the ID/EX register will contain values needed by the ALU in the current cycle, but which are scheduled to be written back to the registers several cycles from now. (309) A. T B. F

A. T

332. It is acceptable to predict not only whether or not the branch is taken, but also the branch target if the branch is taken. (324) A. T B. F

A. T

295. The settings of the multiplexors is how each instruction is processed individually. What unit controls most of the mux settings? (271) A. The control unit. B. The register file C. The program counter D. The ALU E. Instruction memory F. The instruction fetch unit

A. The control unit.

291. How many registers does an R-type instruction read from the register file? (258) A. Two B. Five C. None D. One E. Four F. Three

A. Two

338. Which activity would cause an exception in the earliest pipeline stage? (332) A. Undefined op code B. Data hazard. C. Writing to read-ony memory. D. page fault E. Divide by zero F. Arithmetic overflow G. Unaligned instruction fetch.

A. Undefined op code G. Unaligned instruction fetch.

298. In pipelining, which statement is not true? (273) A. You need duplicate hardware to execute multiple steps at the same time B. Pipelining is not without hazards. C. The steps must be independent so that they can be executed simultaneously D. The speedup of the process (vs non pipelined) is roughly equal to the number of steps E. the overall process must be broken into steps F. The simplest CPU designs have the greatest throughput. G. Excessive speculation leads to wasted energy consumption.

A. You need duplicate hardware to execute multiple steps at the same time F. The simplest CPU designs have the greatest throughput.

305. If, in two adjacent instructions, one produces data needed by the following instruction, what type of hazard can occur? (279) A. Structural B. Data C. Control D. Intentional E. Accidental F. Exception

B. Data

323. If a register is written during a cycle, its contents are not available to be read until the following cycle (313) A. T B. F

B. F

335. If an exception occurs, the program must be terminated (327) A. T B. F

B. F

278. Which is not an element of the MIPS CPU (246) A. Register File B. Flash memory C. Arithmetic Logic Unit D. Interrupt handler E. Instruction Memory F. Data Memory G. Program Counter

B. Flash memory D. Interrupt handler

317. Which pipeline register usually provides data for the ALU? (306) A. MEM/WB B. ID/EX C. IF/EX D. EM/MEM E. IF/ID F. EX/WB

B. ID/EX

325. An instruction is stalled by (315) A. Zeroing the $pc for one cycle B. Making the instruction a NOP C. Suppressing the clock pulse D. Inserting a NOP after the instruction

B. Making the instruction a NOP

308. The Rd of an R-type instruction can be forwarded to an instruction (281) A. Two cycles previous B. One cycle later C. One cycle previous D. In the same cycle

B. One cycle later

307. What is the MIPS solution to a data hazard? (280) A. Inserting a delay slot instruction B. Setting ALU input muxes to obtain data from earlier instructions. C. Rewriting the program to eliminate the hazard. D. Throwing an exception E. Throwing a tantrum. F. Executing a page fault G. Forwarding

B. Setting ALU input muxes to obtain data from earlier instructions. G. Forwarding

320. What do the Forward A and Forward B control signals do? (309) A. Stalls instructions if there is a data hazard. B. Tell the muxes on the inputs to the ALU which inputs should be selected. C. Determine if it is a load or store instruction. D. Tell when the next instruction should be read. E. Forwarding in the case of a data hazard. F. Control the ALU G. Determine whether or not a conditional branch instruction takes the branch.

B. Tell the muxes on the inputs to the ALU which inputs should be selected. E. Forwarding in the case of a data hazard.

334. Which register is used in conjunction with the Exception Program Counter (EPC) to handle MIPS exceptions? (327) A. $zero B. The cause register C. The $a registers D. The program counter E. the return address register F. The $v registers

B. The cause register

333. The origin of an interrupt is (326) A. Spontaneous. B. usually a normal system event C. Something whose occurrance can be anticipated. D. External to the processor E. Unanticipatable. F. In memory G. Called an exception

B. usually a normal system event C. Something whose occurrance can be anticipated.

330. What kind of instruction is ideally put in the delay slot (323) A. An instruction which would be executed only if the branch is not taken. B. Any instruction will do, as long as it can be no-oped. C. An instruction whose execution is independent of the branch being taken or not. D. It doesn't matter. E. In instruction which is independent of the branch. F. An instruction which would be executed only if the branch is taken. G. R-type instructions.

C. An instruction whose execution is independent of the branch being taken or not. E. In instruction which is independent of the branch.

326. What method is not used by the MIPS processor to speed branch handling? (318) A. Using an extra adder to compute branch targets quicker. B. Using a comparator to determine branch outcomes more quickly. C. Avoiding the use of branch instructions D. Predicting branch outcomes.

C. Avoiding the use of branch instructions

341. Static multiple issue is done by the (334) A. Loader B. Processor C. Compiler D. Programmer E. Instruction cache F. Data cache

C. Compile

309. The extra time needed to calculate the result of a branch condition creates a(n) (282) A. Instruction NOPs B. Data hazard C. Control hazard D. Pipeline flush. E. structural hazard F. In-line exception

C. Control hazard

315. When during a clock cycle can data be written to registers? (305) A. The falling edge of the clock cycle. B. During the second half of the clock cycle. C. During the first half of the clock cycle. D. Right after the rising edge of the clock pulse. E. Anywhere in the middle. F. Both on the rising edge and the falling edge of the clock pulse. G. Anywhere, depending on the timing of the strobe.

C. During the first half of the clock cycle. D. Right after the rising edge of the clock pulse.

316. When during a clock cycle can data be read from registers? (305) A. The falling edge of the clock cycle. B. Both on the rising edge and the falling edge of the clock pulse. C. During the second half of the clock cycle. D. Anywhere, depending on the timing of the strobe. E. During the first half of the clock cycle. F. Right after it is written. G. Anywhere in the middle.

C. During the second half of the clock cycle. F. Right after it is written.

303. A major effect of pipelining is (276) A. Larger CPI B. Shorter execution time for single instructions. C. Greater instruction throughput. D. Decreased latency. E. a shorter clock cycle. F. Smaller CPI G. reduced instruction count

C. Greater instruction throughput. E. a shorter clock cycle.

294. Which instruction has a 26-bit immediate field? (270) A. LW B. BEQ C. J D. ADD E. SW F. ADDI

C. J

277. The LW instruction requires that ___ register(s) be read. (245) A. Two B. No C. One D. Three

C. One

336. What prevents an instruction that causes an exception from erroneously writing back to the register file? (328) A. All register writes are inhibited while the exception is being handled. B. A rollback command is issued to the register file. C. Setting WB control lines to zero. D. Instructions which write back to the registers cannot cause exceptions. E. Page faults. F. Hazard logic. G. It is No-oped before it gets to the WB stage.

C. Setting WB control lines to zero. G. It is No-oped before it gets to the WB stage.

314. What is a method of resolving data hazards? (303) A. Starting and Stopping B. Throwing an exception. C. Stalling D. Paging E. Caching F. Forwarding G. Reading and Writing

C. Stalling F. Forwarding

347. A processor that can issue more than one instruction per clock cycle is (339) A. Dynamite. B. Super sized. C. Superscalar. D. Dynamic.

C. Superscalar.

350. Which of the following makes it safe to do out-of-order execution? (341) A. dual-ported memory B. Cache snooping C. The commit unit D. The reservation station

C. The commit unit

285. Which device determines which instruction to read next? (253) A. The instruction Multiplexer B. The Write-back logic C. The program counter D. The control unit. E. The ALU F. The PC G. Memory Access

C. The program counter F. The PC

276. Which is not a feature of the MIPS processor? (244) A. There are only two conditional branch instructions B. The set of arithmetic instructions are simple building-blocks C. The only memory accesses are the load and store instructions. D. Complex instructions are longer (more bytes) than simpler instructions

D. Complex instructions are longer (more bytes) than simpler instructions

302. Which is not a MIPS pipeline stage? (275) A. Execute B. Instruction decode C. Write-back D. Data flush. E. Instruction Decode F. Instruction write G. Memory Access

D. Data flush. F. Instruction write

275. The general name for the unit used to operate on or hold data within a processor is called a(n) (241) A. Register B. memory bank C. Pipeline stage D. Datapath element

D. Datapath element

351. What decreases with more advanced multiple-issue strategies? (343) A. Power supply voltage B. Power consumption C. Throughput D. Energy efficiency

D. Energy efficiency

329. A two-bit predictor has ____ states. (322) A. Two B. One C. Eight D. Four

D. Four

311. What is the correct order of MIPS pipeline stages? (287) A. ID-IF-EX-WB-MEM B. IF-ID-MEM-WB-EX C. ID-EX-MEM-WB-IF D. IF-ID-EX-MEM-WB E. MEM-ID-IF-EX-WB F. EX-MEM-WB-IF-ID

D. IF-ID-EX-MEM-WB

299. The fact that all instructions must be fetched, many instructions require register access and ALU operations led to the idea of (274) A. Data Level Parallelism B. Thread Level Parallelism C. Request Level Parallelism D. Instruction Level Parallelism

D. Instruction Level Parallelism

283. If a state element is not read on every clock edge, (250) A. A multiplexor must be used. B. It must be written to main memory. C. It cannot be read. D. It requires a controls signal to be read.

D. It requires a controls signal to be read.

344. Which is a common way of exposing parallelism in computer code? (338) A. Branch Prediction B. Register renaming C. Data matching D. Loop unrolling.

D. Loop unrolling.

280. MUX is the abbreviation for which device? (247) A. Memory access B. Cache blocks C. Memory storage D. Multiplexer E. Multiplier F. Multicrossfeed

D. Multiplexer

340. Speculative Execution is (333) A. A way to use CPU hardware effectively. B. A system of justice in third-world countries. C. Not needed in superscalar processors. D. One response to control hazards. E. Irreversible. F. Energy efficient. G. A method of achieving high performance in pipelined architectures.

D. One response to control hazards G. A method of achieving high performance in pipelined architectures.

327. In a pipelined processor (320) A. Data hazards are automatically taken care of. B. The speedup is indicated by the number of instructions which can be issued in the same cycle. C. More than one instruction can be in a stage at one time. D. Pipeline registers isolate the stages.

D. Pipeline registers isolate the stages.

293. Which instruction calculates an address with the ALU and then uses that address in main memory? (265) A. SLT B. J C. ADDI D. SW E. BEQ F. LW

D. SW F. LW

324. An instruction is converted to a NOP by (314) A. Jumping forward one instruction B. Incrementing the program counter C. Replacing the instruction op code with zeroes. D. Setting all control lines to zero.

D. Setting all control lines to zero

287. Which device accepts 16-bit immediate data and produces a 32-bit output? (255) A. Program Counter B. Register file C. Arithmetic Logic Unit D. Sign Extender E. The control unit0 F. The hazard detector

D. Sign Extender

306. If a data hazard occurs and there is no way to supply the data an instruction needs to execute, what happens (280) A. A control hazard occurs B. An interrupt occurs. C. Data hazard occurs D. An exception occurs E. Execution is delayed with stalls. F. a pipeline stall occurs. G. A structural hazard occurs.

E. Execution is delayed with stalls. F. a pipeline stall occurs.

290. How many registers does a branch instruction read from the register file? (258) A. None B. Three C. One D. Two E. Five F. Four

D. Two

343. If, in a multiple-issue processor, we wish to issue an ALU and a memory instruction in the same cycle, (336) A. the power supply must be substantially larger. B. memory must be dual-ported. C. no extra hardware is needed. D. the register file must allow up to four registers to be read in the ID stage.

D. the register file must allow up to four registers to be read in the ID stage.

318. How are data hazards detected? (306) A. Determining whether or not there has been a cache miss or page fault. B. Determining whether or not preceding instructions have executed correctly. C. Comparing the destination register of the current instruction with the source registers of previous instructions. D. By counting the number of ccycle since execution began. E. Using instruction-specific information from the pipeline registers. F. Comparing the source registers for the current instruction with destination registers of previous instructions. G. By looking for page faults.

E. Using instruction-specific information from the pipeline registers. F. Comparing the source registers for the current instruction with destination registers of previous instructions.

281. What happens in edge-triggered clocking? (249) A. The clock pulse starts on the falling edge B. Instruction execution determines when the clock pulse starts C. Combinational logic continues after the pulse. D. Reads and writes occur during the clock pulse E. Writes occur on the rising edge of the clock pulse F. State is recorded on the rising edge. G. COmbination logic starts before the pulse.

E. Writes occur on the rising edge of the clock pulse F. State is recorded on the rising edge.