CEA201

True

"Don't care" conditions are when certain combinations of values of variables never occur, and therefore the corresponding output never occurs. a. True b. False

sequential access

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________. a. sequential access b. direct access c. random access d. associative

False

A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS) form. a. True b. False

800 to 1600

A DDR3 module transfers data at a clock rate of __________ MHz. a. 600 to 1200 b. 800 to 1600 c. 1000 to 2000 d. 1500 to 3000

True

A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device. a. True b. False

gate

A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals. a. gate b. decoder c. counter d. flip-flop

A

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence. A. loop buffer B. delayed branch C. multiple stream D. branch prediction

True

A computer must be able to process, store, move, and control data. a. True b. False

F

A control hazard occurs when two or more instructions that are already in the pipeline need the same resource. (T/F)

True

A disadvantage of memory-mapped I/O is that valuable memory address space is used up. a. True b. False

False

A high-level language expresses operations in a basic form involving the movement of data to or from registers. a. True b. False

False

A key characteristic of a bus is that it is not a shared transmission medium. a. True b. False

tag

A line includes a _________ that identifies which particular block is currently being stored. a. cache b. hit c. tag d. locality

virtual addresses

A logical cache stores data using __________. a. physical addresses b. virtual addresses c. random addresses d. none of the above

False

A microcomputer architecture and organization relationship is not very close. a. True b. False

False

A multipoint external interface provides a dedicated line between the I/O module and the external device. a. True b. False

False

A nibble is a grouping of four decimal digits. a. True b. False

False

A number cannot be converted from binary notation to decimal notation. a. True b. False

True

A number of chips can be grouped together to form a memory bank. a. True b. False

True

A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology. a. True b. False

disk cache

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________. a. disk cache b. latency c. virtual address d. miss

software

A sequence of codes or instructions is called __________. a. software b. memory c. an interconnect d. a register

False

A sequence of hexadecimal digits can be thought of as representing an integer in base 10. a. True b. False

True

A static RAM will hold its data as long as power is supplied to it. a. True b. False

delayed load

A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions. a. delayed load b. delayed program c. delayed slot d. delayed register

True

A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external. a. True b. False

False

A vacuum tube is a solid-state device made from silicon. a. True b. False

hardware failure interrupt

A(n) _________ is generated by a failure such as power failure or memory parity error. a. I/O interrupt b. hardware failure interrupt c. timer interrupt d. program interrupt

all of the above

ARM processors are designed to meet the needs of _________. a. embedded real-time systems b. application platforms c. secure applications d. all of the above

True

ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in length. a. True b. False

True

ARM provides a versatile virtual memory system architecture that can be tailored to the needs of the embedded system designer. a. True b. False

True

Addresses are a form of data. a. True b. False

gaps

Adjacent tracks are separated by _________. a. sectors b. gaps c. pits d. heads

True

All DRAMs require a refresh operation. a. True b. False

32-bit

All MIPS R series processor instructions are encoded in a single ________ word format. a. 4-bit b. 8-bit c. 16-bit d. 32-bit

32

All instructions in the ARM architecture are __________ bits long and follow a regular format. a. 8 b. 16 c. 32 d. 64

True

All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions. a. True b. False

True

Almost all RISC instructions use simple register addressing. a. True b. False

True

Although convenient for computers, the binary system is exceedingly cumbersome for human beings. a. True b. False

True

An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations. a. True b. False

peripheral

An I/O device is referred to as a __________. a. CPU b. control device c. peripheral d. register

False

An I/O module cannot exchange data directly with the processor. a. True b. False

True

An I/O module must recognize one unique address for each peripheral it controls. a. True b. False

True

An error-correcting code enhances the reliability of the memory at the cost of added complexity. a. True b. False

True

An interrupt is a hardware-generated signal to the processor. a. True b. False

F

An interrupt is generated from software and it is provoked by the execution of an instruction. (T/F)

radix

Another term for "base" is __________. a. radix b. integer c. position d. digit

True

Any Boolean function can be implemented in electronic form as a network of gates. a. True b. False

I/O mechanisms

Architectural attributes include __________ . a. I/O mechanisms b. control signals c. interfaces d. memory technology used

True

At a top level, a computer consists of CPU, memory, and I/O components. a. True b. False

True

Backward compatible means that the programs written for the older machines can be executed on the new machine. a. True b. False

True

Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance. a. True b. False

False

Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates. a. True b. False

True

Because of the inherent binary nature of digital computer components, all forms of data within computers are represented by various binary codes. a. True b. False

True

Both batch multiprogramming and time sharing use multiprogramming. a. True b. False

True

Both sequential access and direct access involve a shared read-write mechanism. a. True b. False

True

Both the structure and functioning of a computer are, in essence, simple. a. True b. False

True

Bus arbitration makes use of vectored interrupts. a. True b. False

synchronous

CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time. a. synchronous b. asynchronous c. clocked S-R d. timed ripple

False

Cache design for HPC is the same as that for other hardware platforms and applications. a. True b. False

False

Cache is not a form of internal memory. a. True b. False

False

Cache memory is a much faster memory than the register file. a. True b. False

False

Changes in computer technology are finally slowing down. a. True b. False

True

Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures. a. True b. False

False

Claude Shannon, a research assistant in the Electrical Engineering Department at M.I.T., proposed the basic principles of Boolean algebra. a. True b. False

True

Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained. a. True b. False

architecture

Computer _________ refers to those attributes that have a direct impact on the logical execution of a program. a. organization b. specifics c. design d. architecture

False

Computer organization refers to attributes of a system visible to the programmer. a. True b. False

True

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy. a. True b. False

rapid

Computer technology is changing at a __________ pace. a. slow b. slow to medium c. rapid d. non-existent

True

Computers are classified into generations based on the fundamental hardware technology employed. a. True b. False

T

Condition codes facilitate multiway branches. (T/F)

both asynchronous and synchronous

Counters can be designated as _________. a. asynchronous b. synchronous c. both asynchronous and synchronous d. neither asynchronous or synchronous

False

DRAM is much costlier than SRAM. a. True b. False

sectors

Data are transferred to and from the disk in __________. a. tracks b. gaps c. sectors d. pits

A

Decimal "10" is _________ in hexadecimal. a. 1 b. A c. 0 d. FF

1010

Decimal "10" is __________ in binary. a. 1000 b. 0010 c. 1010 d. 0001

True

Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components. a. True b. False

False

During a read or write operation, the head rotates while the platter beneath it stays stationary. a. True b. False

lane

Each data path consists of a pair of wires (referred to as a __________) that transmits data one bit at a time. a. lane b. path c. line d. bus

True

Events in the digital computer are synchronized to a clock pulse so that changes occur only when a clock pulse occurs. a. True b. False

False

External memory is often equated with main memory. a. True b. False

utility

Facilities and services provided by the OS that assist the programmer in creating programs are in the form of _________ programs that are not actually part of the OS but are accessible through the OS. a. utility b. multitasking c. JCL d. logical address

True

Flash memory becomes unusable after a certain number of writes. a. True b. False

unit of transfer

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module. a. access time b. unit of transfer c. capacity d. memory ratio

Quine-McCluskey

For more than four variables an alternative approach is a tabular technique referred to as the _________ method. a. DeMorgan b. Quine-McCluskey c. Karnaugh map d. Boole-Shannon

nibble

Four bits is called a _________. a. radix point b. byte c. nibble d. binary digit

the glass substrate

Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________. a. magnetic read and write mechanisms b. platters c. the glass substrate d. a solid state drive

False

I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes. a. True b. False

True

IBM's System/360 was the industry's first planned family of computers. a. True b. False

SRAM

In a _________, binary values are stored using traditional flip-flop logic-gate configurations. a. ROM b. SRAM c. DRAM d. RAM

False

In a system without virtual memory, the effective address is a virtual address or a register. a. True b. False

True

In a volatile memory, information decays naturally or is lost when electrical power is switched off. a. True b. False

False

In any number, the rightmost digit is referred to as the most significant digit. a. True b. False

True

In general, a decoder has n inputs and 2n outputs. a. True b. False

miss

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory. a. miss b. hit c. line d. tag

load and store

In the ARM architecture only _________ instructions access memory locations. a. data processing b. status register access c. load and store d. branch

True

In the absence of parentheses, the AND operation takes precedence over the OR operation. a. True b. False

most significant digit

In the number 3109, the 3 is referred to as the _________. a. most significant digit b. least significant digit c. radix d. base

least significant digit

In the number 3109, the 9 is referred to as the _________. a. most significant digit b. least significant digit c. radix d. base

none of the above

In the number 472.156 the 2 is the _________. a. most significant digit b. radix point c. least significant digit d. none of the above

postindexing

Indexing performed after the indirection is __________. a. relative addressing b. autoindexing c. postindexing d. preindexing

T

Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity. (T/F)

True

Intel's 4004 was the first chip to contain all of the components of a CPU on a single chip. a. True b. False

True

Interfaces between the computer and peripherals is an example of an organizational attribute. a. True b. False

bytes

Internal memory capacity is typically expressed in terms of _________. a. hertz b. nanos c. bytes d. LOR

False

Interrupts do not improve processing efficiency. a. True b. False

True

It is extremely easy to convert between binary and hexadecimal notation. a. True b. False

False

It is not possible to connect I/O controllers directly onto the system bus. a. True b. False

T

It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired. (T/F)

True

John Mauchly and John Eckert designed the ENIAC. a. True b. False

False

Logical functions are implemented by the interconnection of decoders. a. True b. False

True

Magnetic disks are the foundation of external memory on virtually all computer systems. a. True b. False

False

Managers are users of domains that must observe the access permissions of the individual sections and/or pages that make up that domain. a. True b. False

False

Memory references are faster than register references. a. True b. False

True

Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept. a. True b. False

True

Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide. a. True b. False

True

Negative powers of 10 are used to represent the positions of the numbers for decimal fractions. a. True b. False

True

No single technology is optimal in satisfying the memory requirements for a computer system. a. True b. False

False

Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values. a. True b. False

False

Not all machine languages include numeric data types. a. True b. False

base 2

Numbers in the binary system are represented to the _________. a. base 0 b. base 1 c. base 2 d. base 10

True

One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode. a. True b. False

clock tick

One increment, or pulse, of the system clock is referred to as a _________. a. clock tick b. cycle time c. clock rate d. cycle speed

T

One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline. (T/F)

True

One of the traditional ways of describing processor architecture is in terms of the number of addresses contained in each instruction. a. True b. False

False

Our primary counting system is based on binary digits to represent numbers. a. True b. False

True

Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program. a. True b. False

True

Privileged instructions are certain instructions that are designated special and can be executed only by the monitor. a. True b. False

False

Procedure calls and returns are not important aspects of HLL programs. a. True b. False

False

Procedures do not allow programming tasks to be subdivided into smaller units. a. True b. False

True

Program execution consists of repeating the process of instruction fetch and instruction execution. a. True b. False

True

RAID is a set of physical disk drives viewed by the operating system as a single logical drive. a. True b. False

True

RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance. a. True b. False

1

RAID level ________ has the highest disk overhead of all RAID types. a. 0 b. 1 c. 3 d. 5

True

RAM must be provided with a constant power supply. a. True b. False

False

RDRAM is limited by the fact that it can only send data to the processor once per bus clock cycle. a. True b. False

True

Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address. a. True b. False

False

Register indirect addressing uses the same number of memory references as indirect addressing. a. True b. False

Sun Microsystems

SPARC refers to an architecture defined by ________. a. Microsoft b. Apple c. Sun Microsystems d. IBM

False

SSD performance has a tendency to speed up as the device is used. a. True b. False

constant angular velocity

Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________. a. constant angular velocity b. magnetoresistive c. rotational delay d. constant linear velocity

True

Scheduling and memory management are the two OS functions that are most relevant to the study of computer organization and architecture. a. True b. False

Transistors

Second generation computers used __________. a. integrated circuits b. Transistors c. vacuum tubes d. large-scale integration

False

Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words. a. True b. False

True

Semiconductor memory comes in packaged chips. a. True b. False

True

Swapping is an I/O operation. a. True b. False

False

System software was introduced in the third generation of computers. a. True b. False

fly-by

The 8237 DMA is known as a _________ DMA controller. a. command b. cycle stealing c. interrupt d. fly-by

False

The ABI is the boundary between hardware and software. a. True b. False

D

The ARM architecture supports _______ execution modes. A. 2 B. 8 C. 11 D. 7

first

The ENIAC is an example of a _________ generation computer. a. first b. second c. third d. fourth

vacuum tubes

The ENIAC used __________. a. vacuum tubes b. integrated circuits c. IAS

World War II

The Electronic Numerical Integrator and Computer project was a response to U.S. needs during _________. a. the Civil War b. the French-American War c. World War I d. World War II

control and timing

The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices. a. cycle b. status reporting c. control and timing d. data

True

The IAS is the prototype of all subsequent general-purpose computers. a. True b. False

ENIAC

The _________ was the world's first general-purpose electronic digital computer. a. UNIVAC b. MARK IV c. ENIAC d. Hollerith's Counting Machine

address lines

The __________ are used to designate the source or destination of the data on the data bus. a. system lines b. data lines c. control lines d. address lines

register

The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required. a. direct b. indirect c. register d. displacement

F

The allocation of control information between registers and memory are not considered to be a key design issue. (T/F)

lands

The areas between pits are called _________. a. lands b. sectors c. cylinders d. strips

True

The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address. a. True b. False

True

The basic element of a semiconductor memory is the memory cell. a. True b. False

True

The basic function of a computer is to execute programs. a. True b. False

DE116

The binary string 110111100001 is equivalent to __________. a. DE116 b. C7816 c. FF6416 d. B8F16

True

The cache is capable of handling global as well as local variables. a. True b. False

F

The control unit (CU) does the actual computation or processing of data. (T/F)

T

The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline. (T/F)

data bus

The data lines provide a path for moving data among system modules and are collectively called the _________. a. control bus b. address bus c. data bus d. system bus

10

The decimal system has a base of _________. a. 0 b. 10 c. 100 d. 1000

False

The decimal system has a radix of 100. a. True b. False

True

The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9. a. True b. False

True

The delay by the propagation time of signals through the gate is known as the gate delay. a. True b. False

CAV

The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks. a. SSD b. CAV c. ROM d. CLV

True

The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field. a. True b. False

True

The disadvantage of the software poll is that it is time consuming. a. True b. False

False

The disadvantage of using CAV is that individual blocks of data can only be directly addressed by track and sector. a. True b. False

False

The end user is concerned mainly with the computer's architecture. a. True b. False

stack frame

The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________. a. branch b. stack frame c. pop d. push

T

The exception modes have full access to system resources and can change modes freely. (T/F)

the Pyramid

The first commercial RISC product was _________. a. SPARC b. CISC c. VAX d. the Pyramid

True

The focus of MMX technology is multimedia programming. a. True b. False

True

The head must generate or sense an electromagnetic field of sufficient magnitude to write and read properly. a. True b. False

True

The hierarchical nature of complex systems is essential to both their design and their description. a. True b. False

delay slot

The instruction location immediately following the delayed branch is referred to as the ________. a. delay load b. delay file c. delay slot d. delay register

True

The instruction set is the programmer's means of controlling the processor. a. True b. False

all of the above

The interconnection structure must support which transfer? a. memory to processor b. processor to memory c. I/O to or from memory d. all of the above

split cache

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit. a. logical cache b. split cache c. unified cache d. physical cache

False

The major cost in the life cycle of a system is hardware. a. True b. False

False

The major drawback of the EDVAC was that it had to be programmed manually by setting switches and plugging and unplugging cables. a. True b. False

words

The memory of the IAS consists of 1000 storage locations called __________. a. opcodes b. wafers c. VLSIs d. words

True

The memory transfer rate has not kept up with increases in processor speed. a. True b. False

True

The method of calculating the EA is the same for both base-register addressing and indexing. a. True b. False

True

The method of using the same lines for multiple purposes is known as time multiplexing. a. True b. False

keyboard/monitor

The most common means of computer/user interaction is a __________. a. keyboard/monitor b. mouse/printer c. modem/printer d. monitor/printer

data transfer

The most fundamental type of machine instruction is the _________ instruction. a. conversion b. data transfer c. arithmetic d. logical

True

The most important system program is the OS. a. True b. False

True

The number of bits used to represent various data types is an example of an architectural attribute. a. True b. False

immediate

The only form of addressing for branch instructions is _________ addressing. a. register b. relative c. base d. immediate

AND

The operand ________ yields true if and only if both of its operands are true. a. XOR b. OR c. AND d. NOT

OR

The operation _________ yields true if either or both of its operands are true. a. NOT b. AND c. NAND d. OR

True

The operation of the digital computer is based on the storage and processing of binary data. a. True b. False

True

The operation to be performed is specified by a binary code known as the operation code. a. True b. False

True

The register file employs much shorter addresses than addresses for cache and memory. a. True b. False

True

The register file is on the same chip as the ALU and control unit. a. True b. False

False

The rotating interrupt mode allows the processor to inhibit interrupts from certain devices. a. True b. False

cylinder

The set of all the tracks in the same relative position on the platter is referred to as a _________. a. floppy disk b. single-sided disk c. sector d. cylinder

access time

The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write. a. access time b. gap time c. transfer time d. constant angular velocity

True

The textbook for this course is about the structure and function of computers. a. True b. False

False

The transfer time to or from the disk does not depend on the rotation speed of the disk. a. True b. False

True

The two traditional forms of RAM used in computers are DRAM and SRAM. a. True b. False

NOT

The unary operation _________ inverts the value of its operand. a. OR b. NOT c. NAND d. XOR

False

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit. a. True b. False

False

The unit of transfer must equal a word or an addressable unit. a. True b. False

multicore

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate. a. multicore b. GPU c. data channels d. MPC

True

The value of the mode field determines which addressing mode is to be used. a. True b. False

True

The value to be loaded into the program counter can come from a binary counter, the instruction register, or the output of the ALU. a. True b. False

False

The variety of computer products is exhibited only in cost. a. True b. False

all of the above

The von Neumann architecture is based on which concept? a. data and instructions are stored in a single read-write memory b. the contents of this memory are addressable by location c. execution occurs in a sequential fashion d. all of the above

False

The width of a track is double that of the head. a. True b. False

False

The world's first general-purpose electronic digital computer was designed and constructed at The Ohio State University. a. True b. False

integer

The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________. a. general b. ordinal c. integer d. packed BCD

True

The x86 is equipped with a variety of addressing modes intended to allow the efficient execution of high-level languages. a. True b. False

200 to 600

Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz. a. 200 to 600 b. 400 to 1066 c. 600 to 1400 d. 800 to 1600

True

There are 50 tens in the number 509. a. True b. False

True

There is a tremendous variety of products, from single-chip microcomputers costing a few dollars to supercomputers costing tens of millions of dollars that can rightly claim the name "computer". a. True b. False

memory

There must be ________ instructions for moving data between memory and the registers. a. branch b. logic c. memory d. I/O

False

Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing. a. True b. False

True

Timing refers to the way in which events are coordinated on the bus. a. True b. False

True

To achieve greatest performance the memory must be able to keep up with the processor. a. True b. False

True

To handle any possible pattern of calls and returns the number of register windows would have to be unbounded. a. True b. False

data communications

When data are moved over longer distances, to or from a remote device, the process is known as __________. a. data communications b. registering c. structuring d. data transport

False

When data are moved over longer distances, to or from a remote device, the process is known as data transport. a. True b. False

True

When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA). a. True b. False

double sided

When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________. a. multiple sided b. substrate c. double sided d. all of the above

False

When using graph coloring, nodes that share the same color cannot be assigned to the same register. a. True b. False

write through

When using the __________ technique all write operations made to main memory are made to the cache as well. a. write back b. LRU c. write through d. unified cache

data-processing instructions

Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions? a. data-processing instructions b. branch instructions c. load and store instructions d. extend instructions

all of the above

Which data type is defined in MMX? a. packed byte b. packed word c. packed doubleword d. all of the above

7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100)

Which of the following is correct? a. 25 = (2 x 102) + (5 x 101) b. 289 = (2 x 103) + (8 x 101) + (9 x 100) c. 7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100) d. 0.628 = (6 x 10-3) + (2 x 10-2) + (8 x 10-1)

all of the above

Which stage is required for load and store operations? a. I b. E c. D d. all of the above

T

While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur. (T/F)

True

With a batch operating system the user does not have direct access to the processor. a. True b. False

True

With simple, one cycle instructions, there is little or no need for microcode. a. True b. False

Pentium

With the __________, Intel introduced the use of superscalar techniques that allow multiple instructions to execute in parallel. a. Core b. 8080 c. 80486 d. Pentium

True

With write back updates are made only in the cache. a. True b. False

T

Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy. (T/F)

DDR3

_______ increases the prefetch buffer size to 8 bits. a. CDRAM b. RDRAM c. DDR3 d. all of the above

I/O

_______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user. a. I/O b. Transfer c. Control d. Branch

Multiplexers

________ are used in digital circuits to control signal and data routing. a. Multiplexers b. Program counters c. Flip-flops d. Gates

DDR-DRAM

________ can send data to the processor twice per clock cycle. a. CDRAM b. SDRAM c. DDR-DRAM d. RDRAM

C

________ is used for debugging. A. Direction flag B. Alignment check C. Trap flag D. Identification flag

Cycle stealing

________ is when the DMA module must force the processor to suspend operation temporarily. a. Interrupt b. Thunderbolt c. Cycle stealing d. Lock down

Constant linear velocity (CLV)

________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center. a. Constant angular velocity (CAV) b. Magnetoresistive c. Constant linear velocity (CLV) d. Seek time

Thrashing

________ is when the processor spends most of its time swapping pages rather than executing instructions. a. Swapping b. Thrashing c. Paging d. Multitasking

Soft errors

_________ can be caused by power supply problems or alpha particles. a. Soft errors b. AGT errors c. Hard errors d. SEC errors

D

_________ is a pipeline hazard. A. Control B. Resource C. Data D. All of the above

Orthogonality

_________ is a principle by which two variables are independent of each other. a. Opcode b. Orthogonality c. Completeness d. Autoindexing

C

__________ are a set of storage locations. A. Processors B. PSWs C. Registers D. Control units

Hard errors

__________ can be caused by harsh environmental abuse, manufacturing defects, and wear. a. SEC errors b. Hard errors c. Syndrome errors d. Soft errors

Displacement addressing

__________ has the advantage of flexibility, but the disadvantage of complexity. a. Stack addressing b. Displacement addressing c. Direct addressing d. Register addressing

Indirect addressing

__________ has the advantage of large address space, however it has the disadvantage of multiple memory references. a. Indirect addressing b. Direct addressing c. Immediate addressing d. Stack addressing

DDR2

__________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip. a. DDR2 b. RDRAM c. CDRAM d. DDR3

All of the above

__________ is a design principle employed in designing the PDP-10 instruction set. a. Orthogonality b. Completeness c. Direct addressing d. All of the above

Direct mapping

__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line. a. Direct mapping b. Associative mapping c. Set associative mapping d. None of the above

RAID

__________ is the standardized scheme for multiple-disk database design. a. RAID b. CAV c. CLV d. SSD

Location

__________ refers to whether memory is internal or external to the computer. a. Location b. Access c. Hierarchy d. Tag

router

A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage area network. a. memory controller b. TCA c. HCA d. router

B

A ________ hazard occurs when there is a conflict in the access of an operand location. A. resource B. data C. structural D. control

NOOP

A ________ instruction can be used to account for data and branch delays. a. SUB b. NOOP c. JUMP d. all of the above

target channel adapter

A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch. a. target channel adapter b. InfiniBand switch c. host channel adapter d. subnet

shift register

A _________ accepts and/or transfers information serially. a. S-R latch b. shift register c. FPGA d. parallel register

superpipelined

A _________ architecture is one that makes use of more, and more fine-grained pipeline stages. a. parallel b. superpipelined c. superscalar d. hybrid

FPGA

A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs. a. SPLD b. FPGA c. PAL d. PLA

domain

A _________ is a collection of memory regions. a. APX b. nucleus c. domain d. page table

Blu-ray DVD

A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side. a. DVD b. DVD-R c. DVD-RW d. Blu-ray DVD

system interconnection

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O. a. system interconnection b. CPU interconnection c. peripheral d. processor

job control language

A _________ is a special type of programming language used to provide instructions to the monitor. a. job control language b. multiprogram c. kernel d. utility

physical address

A _________ is an actual location in main memory. a. logical address b. partition address c. base address d. physical address

uniprogramming

A _________ system works only one program at a time. a. batch b. uniprogramming c. kernel d. privileged instruction

ROM

A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it. a. RAM b. SRAM c. ROM d. flash memory

nonremovable

A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer. a. nonremovable b. movable-head c. double sided d. removable

protocol

A __________ is the high-level set of rules for exchanging packets of data between devices. a. bus b. protocol c. packet d. QPI

hierarchical

A __________ system is a set of interrelated subsystems. a. secondary b. hierarchical c. complex d. functional

True

A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside. a. True b. False

True

A branch can be either forward or backward. a. True b. False

unconditional branch

A branch instruction in which the branch is always taken is _________. a. conditional branch b. unconditional branch c. jump d. bi-endian

system bus

A bus that connects major computer components (processor, memory, I/O) is called a __________. a. system bus b. address bus c. data bus d. control bus

False

A characteristic of ROM is that it is volatile. a. True b. False

True

A combinational circuit consists of n binary inputs and m binary outputs. a. True b. False

system bus

A common example of system interconnection is by means of a __________. a. register b. system bus c. data transport d. control device

False

A common measure of performance for a processor is the rate at which instructions are executed, expressed as billions of instructions per seconds (BIPS). a. True b. False

True

A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet. a. True b. False

True

A number with both an integer and fractional part has digits raised to both positive and negative powers of 10. a. True b. False

True

A register is a digital circuit used within the CPU to store one or more bits of data. a. True b. False

True

A removable disk can be removed and replaced with another disk. a. True b. False

True

A set of I/O modules is a key element of a computer system. a. True b. False

True

A wafer is made of silicon and is broken up into chips which consists of many gates and/or memory cells plus a number of input and output attachment points. a. True b. False

high-level language

A(n) _________ expresses operations in a concise algebraic form using variables. a. opcode b. high-level language c. machine language d. register

program interrupt

A(n) _________ is generated by some condition that occurs as a result of an instruction execution. a. timer interrupt b. I/O interrupt c. program interrupt d. hardware failure interrupt

I/O controller

An I/O module that is quite primitive and requires detailed control is usually referred to as an _________. a. I/O command b. I/O controller c. I/O channel d. I/O processor

I/O channel

An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________. a. I/O channel b. I/O command c. I/O controller d. device controller

True

Because the 82C55A is programmable via the control register, it can be used to control a variety of simple peripheral devices. a. True b. False

5

Binary 0101 is hexadecimal _________. a. 0 b. 5 c. A d. 10

False

Binary addition is exactly the same as Boolean algebra. a. True b. False

fetch cycle

During the _________ the opcode of the next instruction is loaded into the IR and the address portion is loaded into the MAR. a. execute cycle b. fetch cycle c. instruction cycle d. clock cycle

indexing

For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address. a. indexing b. base-register addressing c. relative addressing d. all of the above

False

For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits. a. True b. False

access time

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. a. memory cycle time b. direct access c. transfer rate d. access time

immediate

For the _________ mode, the operand is included in the instruction. a. immediate b. base c. register d. displacement

16

Hexadecimal has a base of _________. a. 2 b. 8 c. 10 d. 16

True

Hexadecimal notation is more compact than binary notation. a. True b. False

False

Hexadecimal notation is only used for representing integers. a. True b. False

False

Historically the distinction between architecture and organization has not been an important one. a. True b. False

True

In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay. a. True b. False

512

In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size. a. 64 b. 128 c. 256 d. 512

T

Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed. (T/F)

True

It has become common practice to use a symbolic representation of machine instructions. a. True b. False

True

It has become possible to have a cache on the same chip as the processor. a. True b. False

architectural

It is a(n) _________ design issue whether a computer will have a multiply instruction. a. architectural b. memory c. elementary d. organizational

organizational

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. a. architectural b. memory c. mechanical d. organizational

True

It is common for programs, both system and application, to continue to exhibit new bugs after years of operation. a. True b. False

True

It is the responsibility of the processor to periodically check the status of the I/O module until it finds that the operation is complete. a. True b. False

True

One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set. a. True b. False

RAM

One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly. a. RAM b. ROM c. EPROM d. EEPROM

True

RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations. a. True b. False

True

The IAS operates by repetitively performing an instruction cycle. a. True b. False

False

The Intel x86 evolved from RISC design principles and is used in embedded systems. a. True b. False

False

The L1 cache is slower than the L3 cache. a. True b. False

64

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU. a. 16 b. 32 c. 64 d. 128

page table

The OS maintains a __________ for each process that shows the frame location for each page of the process. a. kernel b. page table c. TLB d. logical address

True

The OS must determine how much processor time is to be devoted to the execution of a particular user program. a. True b. False

A

The OS usually runs in ________. A. supervisor mode B. abort mode C. undefined mode D. fast interrupt mode

HLL

The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture. a. HLL b. RISC c. CISC d. all of the above

execution unit

The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers. a. fetch/decode unit b. out-of-order execution logic c. execution unit d. memory subsystem

True

The Pentium II includes hardware for both segmentation and paging. a. True b. False

routing

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects. a. link b. protocol c. routing d. physical

8

The R4000 can have as many as _______ instructions in the pipeline at the same time. a. 8 b. 10 c. 5 d. 3

write back

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage. a. write back b. tag check c. data cache d. instruction execute

False

The SRAM on the CDRAM cannot be used as a buffer to support the serial access of a block of data. a. True b. False

True

The SSDs now on the market use a type of semiconductor memory referred to as flash memory. a. True b. False

all of the above

The TL supports which of the following address spaces? a. memory b. I/O c. message d. all of the above

physical

The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer. a. cable b. application c. common transport d. physical

control

The ________ command is used to activate a peripheral and tell it what to do. a. control b. test c. read d. write

memory cycle time

The ________ consists of the access time plus any additional time required before a second access can commence. a. latency b. memory cycle time c. direct access d. transfer rate

application

The ________ contains I/O protocols that are mapped on to the transport layer. a. cable b. application c. common transport d. physical

A

The ________ controls the movement of data and instructions into and out of the processor. A. control unit B. ALU C. shifter D. branch

A

The ________ determines the opcode and the operand specifiers. A. decode instruction B. fetch operands C. calculate operands D. execute instruction

buffer

The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible. a. flash memory b. Hamming code c. RamBus d. buffer

flip-flop

The ________ exists in one of two states and, in the absence of input, remains in that state. a. assert b. complex PLD c. decoder d. flip-flop

J-K

The ________ flip-flop has two inputs and all possible combinations of input values are valid. a. J-K b. D c. S-R d. clocked S-R

API

The ________ gives a program access to the hardware resources and services available in a system through the user instruction set architecture supplemented with high-level language library calls. a. JCL b. ISA c. ABI d. API

common transport

The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology. a. cable b. application c. common transport d. physical

short-term

The ________ scheduler is also known as the dispatcher. a. long-term b. medium-term c. short-term d. I/O

opcode

The ________ specifies the operation to be performed. a. source operand reference b. opcode c. next instruction reference d. processor register

write

The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral. a. control b. test c. read d. write

C

The _________ contains a word of data to be written to memory or the word most recently read. A. MAR B. PC C. MBR D. IR

I/O module

The _________ contains logic for performing a communication function between the peripheral and the bus. a. I/O channel b. I/O module c. I/O processor d. I/O command

D

The _________ contains the address of an instruction to be fetched. A. instruction register B. memory address register C. memory buffer register D. program counter

ISA

The _________ defines the repertoire of machine language instructions that a computer can follow. a. ABI b. API c. HLL d. ISA

ABI

The _________ defines the system call interface to the operating system and the hardware resources and services available in a system through the user instruction set architecture. a. HLL b. API c. ABI d. ISA

SDRAM

The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. a. DDR-DRAM b. SDRAM c. CDRAM d. none of the above

skip

The _________ instruction includes an implied address. a. skip b. rotate c. stack d. push

C

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline. A. dynamic branch B. loop table C. branch history table D. flag

transaction layer

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. a. transaction layer b. root layer c. configuration layer d. transport layer

long-term

The _________ scheduler determines which programs are admitted to the system for processing. a. long-term b. medium-term c. short-term d. I/O

B

The _________ stage includes ALU operations, cache access, and register update. A. decode B. execute C. fetch D. write back

main memory

The _________ stores data. a. system bus b. I/O c. main memory d. control unit

binary

The _________ system uses only the numbers 0 and 1. a. positional b. binary c. hexadecimal d. decimal

excitation

The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit. a. excitation b. Kenough c. J-K flip-flop d. FPGA

PDP-11

The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer. a. PDP-1 b. PDP-8 c. PDP-11 d. PDP-10

SIB

The __________ byte consists of three fields: the Scale field, the Index field and the Base field. a. SIB b. VAX c. PDP-11 d. ModR/M

instruction register

The __________ contains the 8-bit opcode instruction being executed. a. memory buffer register b. instruction buffer register c. instruction register d. memory address register

integrated circuit

The __________ defines the third generation of computers. a. integrated circuit b. vacuum tube c. transistor d. VLSI

control unit

The __________ interprets the instructions in memory and causes them to be executed. a. main memory b. control unit c. I/O d. arithmetic and logic unit

operating system

The __________ is a program that controls the execution of application programs and acts as an interface between applications and the computer hardware. a. job control language b. operating system c. batch system d. nucleus

speed metric

The __________ measures the ability of a computer to complete a single task. a. clock speed b. speed metric c. execute cycle d. cycle time

I/O

The __________ moves data between the computer and its external environment. a. data transport b. I/O c. register d. CPU interconnection

ALU

The __________ performs the computer's data processing functions. a. Register b. CPU interconnection c. ALU d. system bus

False

The address of the next instruction to be fetched must be a real address, not a virtual address. a. True b. False

False

The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device. a. True b. False

immediate addressing

The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand. a. direct addressing b. immediate addressing c. register addressing d. stack addressing

T

The predict-never-taken approach is the most popular of all the branch prediction methods. (T/F)

True

The prefetch buffer is a memory cache located on the RAM chip. a. True b. False

direct

The principal advantage of ___________ addressing is that it is a very simple form of addressing. a. displacement b. register c. stack d. direct

True

The principal price to pay for variable-length instructions is an increase in the complexity of the processor. a. True b. False

instruction

The processing required for a single instruction is called a(n) __________ cycle. a. execute b. fetch c. instruction d. packet

T

The processor needs to store instructions and data temporarily while an instruction is being executed. (T/F)

True

The processor requires its own local memory. a. True b. False

True

There are typically hundreds of sectors per track and they may be either fixed or variable lengths. a. True b. False

False

Typically an instruction set will include both preindexing and postindexing. a. True b. False

False

Uniprogramming is the central theme of modern operating systems. a. True b. False

True

Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance. a. True b. False

TLB

Virtual memory schemes make use of a special cache called a ________ for page table entries. a. TLB b. HLL c. VMC d. SPB

John von Neumann

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton. a. John Maulchy b. John von Neumann c. Herman Hollerith d. John Eckert

7

Which digit represents "hundreds" in the number 8732? a. 8 b. 7 c. 3 d. 2

all of the above

Which of the following interrelated factors go into determining the use of the addressing bits? a. number of operands b. number of register sets c. address range d. all of the above

all of the above

Which of the following is a functionally complete set? a. AND, NOT b. NOR c. AND, OR, NOT d. all of the above

all of the above

Which of the following is a true statement? a. a procedure can be called from more than one location b. a procedure call can appear in a procedure c. each procedure call is matched by a return in the called program d. all of the above

all of the above

Which of the following memory types are nonvolatile? a. erasable PROM b. programmable ROM c. flash memory d. all of the above

all of the above

Which properties do all semiconductor memory cells share? a. they exhibit two stable states which can be used to represent binary 1 and 0 b. they are capable of being written into to set the state c. they are capable of being read to sense the state d. all of the above

flash memory

With _________ the microchip is organized so that a section of memory cells are erased in a single action. a. flash memory b. SDRAM c. DRAM d. EEPROM

unsegmented unpaged memory

With _________ the virtual address is the same as the physical address. a. unsegmented unpaged memory b. unsegmented paged memory c. segmented unpaged memory d. segmented paged memory

False

With a daisy chain the processor just picks the interrupt line with the highest priority. a. True b. False

False

With asynchronous timing the occurrence of events on the bus is determined by a clock. a. True b. False

False

With demand paging it is necessary to load an entire process into main memory. a. True b. False

True

With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range. a. True b. False

False

With isolated I/O there is a single address space for memory locations and I/O devices. a. True b. False

Logic

________ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ. a. Logic b. Arithmetic c. Memory d. Test

DisplayPort

________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces. a. DisplayPort b. PCI Express c. Thunderbolt d. InfiniBand

Read only memory

________ is implemented with combinational circuits. a. Nano memory b. Random access memory c. Read only memory d. No memory

B

________ registers may be used only to hold data and cannot be employed in the calculation of an operand address. A. General purpose B. Data C. Address D. Condition code

Organizational

_________ attributes include hardware details transparent to the programmer. a. Interface b. Organizational c. Memory d. Architectural

Execution sequencing

_________ determines the control and pipeline organization. a. Calculation b. Execution sequencing c. Operations performed d. Operands used

Load-and-store

_________ instructions are used to position quantities in registers temporarily for computational operations. a. Load-and-store b. Window c. Complex d. Branch

Arithmetic

_________ instructions provide computational capabilities for processing number data. a. Boolean b. Logic c. Memory d. Arithmetic

Register storage

_________ is the fastest available storage device. a. Main memory b. Cache c. Register storage d. HLL

Registers

_________ provide storage internal to the CPU. a. Control units b. ALUs c. Main memory d. Registers

B

__________ are bits set by the processor hardware as the result of operations. A. MIPS B. Condition codes C. Stacks D. PSWs

direct access

individual blocks or records have a unique address based on physical location with __________. a. associative b. physical access c. direct access d. sequential access