CH 03: LOGIC GATES AND GATE COMBINATIONS: KEY TERMS

Target device

A PLD mounted on a programming fixture or development board into which a software logic design is to be downloaded.

Timing diagram

A diagram of waveforms showing the proper timing relationship of all the waveforms.

Inverter

A logic circuit that inverts or complements its input.

NOR gate

A logic gate in which the output is LOW when one or more of the inputs are HIGH.

AND gate

A logic gate that produces a HIGH output only when all of the inputs are HIGH.

Exclusive-OR (XOR) gate

A logic gate that produces a HIGH output only when its two inputs are at opposite levels.

OR gate

A logic gate that produces a HIGH output when one or more inputs are HIGH.

Exclusive-NOR gate

A logic gate that produces a LOW only when the two inputs are at opposite levels.

NAND gate

A logic gate that produces a LOW output only when all the inputs are HIGH.

Unit load

A measure of fan-out. One gate input represents one unit load to the output of a gate within the same IC family.

VHDL

A standard hardware description language that describes a function with an entity/architecture structure.

Verilog

A standard hardware description language that uses a module structure to describe a function.

Variable

A symbol used to represent an action, a condition, or data that can have a value of 1 or 0, usually designated by an italic letter or word.

Truth table

A table showing the inputs and corresponding output(s) of a logic circuit.

EPROM

A type of PLD nonvolatile programmable link based on electrically programmable read-only memory cells and can be turned either on or off once with programming.

Antifuse

A type of PLD nonvolatile programmable link that can be left open or can be shorted once as directed by the program.

Fuse

A type of PLD nonvolatile programmable link that can be left shorted or can be opened once as directed by the program.

Flash

A type of PLD nonvolatile reprogrammable link technology based on a single transistor cell.

SRAM

A type of PLD volatile reprogrammable link based on static random-access memory cells and can be turned on or off repeatedly with programming.

EEPROM

A type of nonvolatile PLD reprogrammable link based on electrically erasable programmable read-only memory cells and can be turned on or off repeatedly by programming.

AND array

An array of AND gates consisting of a matrix of programmable interconnections.

Product term

The Boolean product of two or more literals equivalent to an AND operation.

Sum term

The Boolean sum of two or more literals equivalent to an OR operation.

Complement

The inverse or opposite of a number. In Boolean algebra, the inverse function, expressed with a bar over a variable. The complement of a 1 is 0, and vice versa.

Boolean algebra

The mathematics of logic circuits.

Fan-out

The number of equivalent gate inputs of the same family series that a logic gate can drive.

Propagation delay time

The time interval between the occurrence of an input transition and the occurrence of the corresponding output transition in a logic circuit.

JTAG Joint Test Action Group;

an interface standard designated IEEE Std. 1149.1.