Combinational Logic
consensus theorem (to eliminate redundant variables)
(B * C) + (B bar * D) + (C * D) = B * C + B bar * D Dual: (B + C) * (B bar + D) * (C + D) = (B + C) * (B bar + D) all three variables appear in permutation pairs, one is complemented
combining theorem (to eliminate redundant variables)
(Β • C) + (B • C bar) = Β Dual: (B + C) • (B + C bar) = B
associativity
(Β • C) • D = Β • (C • D) Dual: (B + C) + D = B + (C + D)
normal term
+ or * where all literals appear once
tristate buffer
3 possible states (HIGH, LOW, Z) input A output Y enable E (when True, buffer acts as simple, otherwise, output floats to Z) active low: put bubble on wire or put bar over name usage: busses, where one chip at a time asserts enable signal to drive value onto bus, all other chips float to not disrupt information flow
OR gate
A + B, A OR B output is zero only if all inputs are zero
combinational circuit
A circuit whose output is solely determined by its input values memoryless ex. logic gate
AND gate
A dot B, A AND B, AB output is 1 only if all inputs are a 1
distributivity
AND distributes over OR and vice versa (Β • C) + (Β • D) = Β • (C + D) Dual: (B + C) • (B + D) = B + (C • D)
sum of products as NAND
AND going into OR is the same as AND NOT NOT OR which is the same as NAND NAND
complements
B * bar B = 0 Dual: B + bar B = 1
null element theorem
B AND 0 is 0 0 is null element of AND(nullifies effect of any other input) Dual: B OR 1 is 1
identity theorem
B and 1 = B Dual: B OR 0 = B
idempotency
B*B = B Dual: B + B = B
buffer gate
BUF regular triangle one-input logic gate 0--> 0 1 --> 1 from analog point of view, buffer can deliver large amounts of current to motor or deliver output to many gates
5 axioms of boolean algebra (with NOT axiom in parentheses)
Binary field: B = 0 if B is not 1 (B = 1 if B is not 0 ) NOT: 0 bar = 1 (1 bar = 0) A3: 0 * 0 = 0 (1 + 1 = 1) A4: 1 * 1 = 1 (0 + 0 = 0) A5: 0 * 1 = 1* 0 = 0 (1 + 0 = 0 + 1 = 1)
K-map tricks
Grab the corners! Remember wrap around (top to bottom, right to left)
boolean operation precedence
High to low NOT > AND > OR
Decoder
N inputs, 2^N outputs asserts exactly one of its outputs (one-hot) can be implemented as AND gates for minterms (outputs are minterms) (ADD OR GATES to get function representations) N-input func and M 1's can be built with N: 2 ^N decoder or M-input OR gate attached to all minterms containing 1's in truth table **if you have variables missing in minimized expression just treat it as unminimized
in CMOS
NAND and NOR are preferred
NAND gate
NOT AND output is true unless both inputs are true equivalent to OR gate with inverted inputs
NOR gate
NOT OR equivalent to AND gate with inverted inputs
product of sums as NOR
ORs going into an A is the same as OR NOT NOT AND which is the same as NOR NOR
gray code
Only one digit changes each time a new value is displayed 00 -> 01 -> 11 -> 10
XOR gate
Outputs 1 when inputs are different (this is certainly true for 2 input, but for N-input, interpretations vary) (Exclusive OR) >> FOR THIS COURSE remember that it is true when ODD # is TRUE (excludes when inputs are the same, odd one out is zero) + sign in a bubble N-input XOR gate is sometimes called parity gate, producing true if an ODD # of inputs are true (so for 3 inputs, 1 xor 1 xor 1 = 1), implemented by cascading 2-input XOR gates
programmable logic array
PLA, systemic fashion of arranging inverters, AND, OR
demorgan's theorem
Theorem stating that the complement of a sum (OR operation) equals the product (AND operation) of the complements, and theorem stating that the complement of a product (AND operation) equals the sum (OR operation) of the complements.
NOT gate
X', X bar, /X, NOT X inverter 0 -> 1 1 --> 0
element
a circuit with inputs outputs and spec
node
a wire whose voltage conveys discrete valued variables either input, output or internal
tristate driver
along with 0 and 1 ther eis third HI-Z output output floats (no connection to supply/ground) has EN input too output HI-Z only happens when EN = 0 useful for multidrop buses (imagine devices all in line to one input line....let others float except for the device driving the bus)
complement of variable A
bar A, inverse
binary system
base 2 values 0 and 1 basic unit of information: binary digit, or bi t advantages: simplest circuits, lowest power disadvantage: highest # of positions needed to rep large #s
bus
bundle of multiple signals line with slash through it, with a # specifying the number of signals in the bus
multiplexer logic
can mimic a truth table/function... let inputs be 00, 01, 10, etc. and output be whatever truth table should output simplify by combining rows input wires can be Z, B, Z not etc. can simplify by changing which column gets to be the selector too (DOES NOT ALWAYS HAVE TO BE LAST COLUMN!) then you might get away with not using any inverters
supply voltage
comes from power supply Vdd lowest voltage is 0 V (ground or GND)
converting ANDS and ORs to NANDs and NORs
could add inverter to everything....but better way is to just observe that NOT output --> NOT input cancels out wo affecting the function!! and then INVERT anything that is output/input of whole circuit
schematic
diagram of digital circuit showing elements and wires connecting them together top or left: inputs right or bottom: outputs gates flow left to right if possible wires connect at a T junction dot where wires cross indicates connection bw wires, no dot = no connection
involution
double bar B = B
5-variable K-map
draw two 4-variable maps for which last variable = 0 and last variable = 1 for other map where the two maps overlap is where you can eliminate the last variable then do K-map terms as normal for other stuff TWO TYPES: overlaid (i.e. right next to each other, gray code order!) mirrored (flip like a book to find overlaps)
sum of products form aka canonical sum(not necessarily the same as a regular sum of products)
each row in a truth table has a minterm that is TRUE for that row can write boolean equation for any truth table by summing each of minterms for which output Y (not minterm output) is TRUE << sum of products canonical form of function can be written as sigma notation (replace sum with sigma)
product of sums form aka canonical product (not the same as a regular product of sums)
each row of truth table corresponds to maxterm that is FALSE for that row boolean eq = AND of each maxterms for which output is FALSE may use PI notation
use of XOR
equality comparator 0 if the inputs are same
circuit is combinational if
every circuit element is itself combinational every node of the circuit is either designated as an input to circuit or connects to exactly one output terminal of a circuit element circuit contains no cyclic paths (every path thru circuit visits each circuit node at most once)
get canonical product from K-Map
find all the zero's circle those remember to write as sums, and then you want sums to be zero!
digital system
finite # of values
how logic levels work
first gate (driver) outputs to input of second gate (receiver) output of driver between 0 V to V IL = LOW interpretation by receiver output of driver between V IH to VDD = HIGH interpretation by receiver if for some reason receiver's input falls in forbidden (between VIL and VIH) zone, behavior is unpredictable
logic gate
fundamental digital system building block takes one or more binary inputs to produce binary output
priority encoder
highest number inputs have priority Ignores problem with encoder where you have more than one high input it gets confused...this one prioritizes higher binary value!
prime implicant
if it cannot be combined with any other implicants to form a new implicant w fewer literals
boolean principles of duality
if symbols 0 and 1 and operators AND and OR are interchanged in axioms/theorems, statement is still right --> but you DO NOT need to complement or change the literals (B, X, Y etc) Make sure to first add parentheses to denote operator precedence and THEN switch your #'s, logic gates ' (prime) denotes dual of statement ex. X + X * Y = X X + (X*Y) = X X * (X+Y) = X is the dual of the first statement
XNOR gate
inverse of XOR output is true when inputs are equal aka equality gate for 2-input gate
positional number representation
leftmost is 2^0 * digit 101 = 1 x 2^2 + 0 x 2^1 + 1 x 2^0 = 5 (decimal equivalent)
two-level logic
logic in sum-of-products form
how to represent more than 2 values
multiple bits 2 bits = 4 possible values n bits = 2^n possible values, meaning decimals from 0 to 2^n - 1
circuit
network that processes discrete valued variables, composed of nodes and elements has input terminals output terminals functional spec describing relationship bw inputs/outputs timing specification describing delay bw inputs changing and outputs responding
floating value Z
node is floating, high impedance, or high Z (neither HIGH nor LOW) thus, cannot assume unconnected input = 0, it is floating Z
minterm
normal product involving all inputs to the function (results in a 1)
encoder
opp of decoder 2^N inputs and n outputs (binary value indicated which input = 1) does NOT have a select input, mux DOES
commutativity
order of inputs for AND or OR doesn't matter B*C = C*B Dual: B+C=C+B
sequential circuit
output depends on both current and previous values of inputs has memory
XAND gate
outputs 1 when inputs are the same (excludes when inputs are the same, odd one out is 1)
karnaugh map visual representation of
ovals result from applying combining theorem overlap in circles comes from idempotency theorem GOAL: cover w min number of prime implicants
NAND with p-n type transistors
p type goes in parallel on top and the n type goes in series
NOR with n-p type transistors
p type is always in series on top and the n type is always in parallel on the bottom
N-input OR
produces TRUE output when at least 1 input is TRUE
N-input AND
produces true when all N inputs are TRUE
AND
product or implicant
FPGA (Field Programmable Gate Array)
programmable logic device; series of chips or logic gates that can be programmed
bubble pushing
pushing bubbles through gate turns it from AND to OR (or vice versa) and puts bubbles on all inputs/outputs (depending on pushing direction) for logic circuits...use bubble processing to read function from NAND and NORs (CMOS logic)...use this to derive SOP form and get ANDs/ORs 1. go from output to input 2. push gate output bubbles to inputs 3. draw each gate so bubbles cancel (if current gate has input bubble, draw preceding w output...otherwise, draw wo output)...........SO START FROM OUTPUT! EITHER BUBBLES CANCEL or NO BUBBLES BW GATES
numbers in digital systems
represented by discrete voltage levels, need spacing of ~1V to account for electronic noise
decoder applications
select one of n rows of memory cells to read/write instruction decoding: determine type of instruction (ADD, etc) based on n-bit binary code w the instruction input/output systems: select one of n input/output devices to read/write
multiplexers (mux)
selects output from several possible inputs based on SELECT signal if S = 0, Y = D0, if S = 1, Y = D1 can be built with sum of products or tristate buffers N:1 multiplexer needs log2 N select lines
karnaugh map implicant
set of adjacent 1-cells (must be power of 2) prime implicant: implicant that can't be contained in a larger implicant distinguished 1-cell: 1-cell covered by only one prime implicant (essential prime implicant)
maxterm
sum involving all inputs to a function (normal, results in a zero)
OR
sum of 1 or more literals
minimized equation
sum of products is minimzed when it has fewest possible # of implicants if same # implicants for many, choose one with fewest literals must have all prime implicants tip: expand elements REMEMBER YOU CAN ALWAYS DUPLICATE necessary terms using idempotency theorem!
base 1 system
tally marks: each tally = 1 so 7 is 1111111 this is because base b representation doesn't work for b < 2 (i.e. if we did base 1, then the only digit is 0, meaning all #s would be 0)
illegal value X
unknown value, i.e. when driven to HIGH and LOW simultaneously (this situation is called contention) X is also used in truth table to indicate "don't cares"
karnaugh maps
up for 4 variables...at most 2 in a pair (columN) each square represents a single minterm "wraps around" columns (AB-> 00 01 11 10 ) etc. rows are C (0 and 1) allows us to quickly do/find cancellations like AB(C + C bar) = AB we can circle items with 1's in the squares, thus cancelling those out USE FEWEST # CIRCLES(largest possible), where each circle must span rectangular block that's power of 2 Circles can wrap around edges of K-map X's CAN BE CIRCLED A 1 in a K-map can be circled many times if this causes fewer circles to be used (AS MANY OVERLAPS AS POSSIBLE) BUT ALSO FEWEST CIRCLES (so if ur circling stuff that's already been circled it's not helping) if true form and complementary form appear in different columns in the circle, then it DISAPPEARS!
literal
variable or its complement Where A is the true form, bar A is complementary form
0 and 1 are represented by
voltage ranges (logic levels) --> mapping continuous variable to discrete binary variable 0.8-1 V = 1 0 - 0.2 V = 0 due to electronic noise
decoder w enable
when EN = 1, acts like regular encoder with EN= 0, all outputs are 0
perfect induction
where observe every member of group to make conclusions
base 10 system in electronics
would need 0-9 V advantages: low # pos need to rep #s Disadvantages: complex circuits, high required voltage
how to convert to NANDs/NORs
you put equation in terms of ANDs and ORs, then cancel out inputs/outputs by NOTing both (think in between) and then doing bubble pushing...
covering theorem (to eliminate redundant variables)
Β • (Β + C) = Β Dual: B + (B • C) = B
