CS 252 FINAL

how is an interrupt signal generated from KBSR

- bit 15 is the 'ready' bit - bit 14 is the 'interrupt enable' bit - code sets the 'interrupt enable' bit in the DSR through the global data bus - bits 14 and 15 are both connected to an AND gate, so when they are both set to one, an interrupt signal can be sent to the address control logic

does the user's program set the value in a device's data register directly? its status register?

- both are accessible and used by the program - the status register is not changed by the program directly. it is automatically set to zero while info is being processed and back to one when the device is ready to input/output more data - the data register is changed directly in some cases, the program can provide data to the DR to output. an input device will change the DR itself, and the program simply loads its contents when given the signal

I/O controller parts, purpose, inputs and outputs

- enables the processor to communicate with a particular device - receives input from the device - outputs both the input data to and a control/status signal to/from the processor - parts: control register, status register, data register. - the device does the actual io, not the controller, which acts as a go-between for info transfer

LC3 assembler generate machine code process

- for each executable/valid AL instr, generate the machine code - if an operand has a label in the instr, lookup the address of the label and calculate offset from current location - this step is where errors can be found, ie wrong number/type of operands, too large operands, operand's address is too far from PC (relative addressing used for the jumps to labels)

KBSR vs KBDR

- keyboard status register: bit 15 indicates whether or not a new character has been typed - keyboard data register: bits 0-7 have the last character typed (8-15 always zero)

how do you access device registers (io controller, lc3)

- registers are all memory mapped - I/O instructions are designated by the ISA which will encode specific device register/action - these instructions can be called in a program

memory mapped registers

- used by lc3 - actual registers are not used for the io controller for a device, memory addresses are assigned for each register - use instructions that access memory in order to access data (load/store operations) - used for control status and data transfer

display output steps LC-3

1. program sees bit 15 in SR is 1, so writes a char to bits 0-7 of DR 2. SR set to 0 (any attempt to write to DR is now ignored) 3. the contents of the DR are sent out to the device for display 4. the SR bit is set back to 1 (ready for next char)

general flow of execution with interrupts

1. the device sends interrupt signal to the processor (only if the processor has device interrupt enabled) 2. the currently executing program is paused ONLY if that program has a lower priority than the interrupt 3. interrupt service routine is run (privileged) 4. the program resumes as if nothing happened

keyboard input steps LC-3

1. user types a character: the ascii code is loaded into bits 0-7 of KBDR, KBSR bit 15 set to one, keyboard disabled 2. programs sees new char is ready by checking KBSR, and reads KBDR, after which KBSR bit 15 is set to zero and the keyboard is enabled.

describe the lc3 assembler's process

2-pass assembler: scans over the assembly language twice. on the first pass it constructs the symbol table, on the second it generates the machine code

assembler

A program that translates an assembly-language program into machine code, which it stores in an object file (.py or .c or .java -> .asm -> .obj

JSR

Jump to subroutine - save PC (points to instr after SR call) into R7 - change PC using PC-relative with given offset - target address must be within range for offset addressing

LC-3 priority levels

PL0 (lowest) - PL7 (highest). a device with a certain PL can only interrupt programs with lower priority levels that its own

keyboard input polling routine code

POLLin LDI R0, KBSRaddr BRzp POLLin LDI R0, KBDRaddr ... KBSRaddr .FILL xFE00 KBDRaddr .FILL xFE02 (load the contents of the SR into a register, if the result is not negative keep checking. once it is negative, that means SR bit 15 = 1, so load the contents of the DR into a register for use)

output polling routine

POLLout LDI R1, DSRaddr BRzp POLLout STI R0, DDRaddr ... DSRaddr .FILL xFE04 DDRaddr .FILL xFE06 (load the contents of the SR into a register, if the result is not negative keep checking. once it is negative, that means SR bit 15 = 1, so store the desired output to the DDRaddr)

what is required when a program consists of several obj files

a linker

describe the differences between an asm and obj file in lc3

asm = assembly language. ie "AND R1, R1, #0" obj = machine language. ie the 16 bit instruction codes, I think written in ascii

steps of execution of a subroutine

call (aka invoke): sends control to the subroutine execute: do the task return: sends control back to the calling code

priority encoder

compares the priorities of interrupting device and current program. If multiple devices interrupt at once, the priority encoder selects the highest priority device

object file format

contains a starting address where program is loaded, followed by machine instructions. does not have to be a complete program, a program can consist of several obj files

source file

contains high level language

DSR vs DDR

display status register: bit 15 is 1 when ready for next character display data register: bits 0-7 have next char to display

echoing

displaying the character a user has just typed. can implement by using an input polling routine followed by an output polling routine.

example of devices that do input and output

ethernet, wifi, usb, bluetooth

incrementing the LC in symbol table construction

increment by one after viewing a line, unless the directive is something line .BKLW, which allocates space for a block of words, or .stringz

steps for assembler to create the symbol table

initialize the location counter (LC) with the starting addy from the .ORIG directive. for each nonempty line, if a label/symbol is located, store its label and hex memory location in the table, then increment LC, stopping at .END directive

4 types of I/O devices

input, output, input & output, storage

address control logic input and output

input: determines if MDR should be loaded with memory or device registers output: determines if MDR should be loaded with the DSR, or if DDR should be loaded with data through the MDR - knows based on the address coming in whether to access memory or an I/O device register.

the AL instruction is branch to label A, what will the MC instruction look like?

it will be this but the actual binary representation of it: BRnzp, PC offset = distance from current PC

JSRR

jump to subroutine using register addressing mode - save PC into R7 - go to the address contained in the specified base register

LDI

load the contents of a memory location specified by the instructions at a label in the instruction. the specified label must exist in memory, and should follow the form = LABEL .FILL xABCD, where the hex is the desired memory location to access

Machine code vs Assembly code

machine code will be the actual 16 bit instructions, assembly language is the "AND R1, R1, #0"

what does the linker receive as input and produce as output?

obj files as input (binary generated from compiling), to executable code that the cpu can directly use

opcodes vs operations

opcode - 0001 (machine lang instr) operation - ADD (assembly lang instr)

polling, advantages

processer repeatedly checks a status register (SR bit 15 = 1) until new data arrives from the input device or the output device is ready for more data. - advantage: simple to implement

data register

processor reads from and writes to the io controller's data register to transfer data to and from the io device

status register

processor reads from the io devices status register to determine the device's condition (finished with task, currently doing task etc)

control register

processor writes into it to tell the I/O controller what I/O task to do

Assembler Directives

pseudo-instructions used by the ASSEMBLER instead of the processor (trap vectors aka GETC, HALT, etc, also .BKLW, .FILL, .END

what do we need to know about a subroutine in order to use it?

purpose, location, arguments, return value. DON'T NEED TO KNOW SPECIFICS OF IMPLEMENTATION

two steps to linking

resolution: linker checks that each symbol is only defined once relocation: determine all symbols' addresses and complete the machine code with that info

saving/restoring

saving: storing a copy of a registers val in memory restoring: loading a saved value from memory back into its register

symbol in LC-3

specific to LC-3, refers to labels in assembly code (ie LOOP, MOREmm, any address you want to mark off specifically)

data rate

speed of info/data transfer, typically measured as bps (bits per sec) or Bps (bytes per sec)

linking

stitches together symbols (aka labels/names for instructions) used in one object file to their definitions in other obj files

external symbol

symbol used in a file but not defined in it

system vs user memory (lc3 and general)

system memory is automatically loaded with system routines. An lc3 example of a system routine is halt, and system memory is x0000 to x2FFF. user memory is open and to be used to load user code into. in lc3 this goes from x3000 to xFDFF

interrupts

the device signals the processor when new data arrives from input device/output device is ready for more data. - advantage: frees up the CPU to do tasks, which is advantageous especially when input is slow/non-continuous (keyboard vs microphone)

loading

the loader copies the contents of an executable file, produced by the linker, into memory at the specified origin so it can be run

how does the processor determine an interrupt occurred?

the regular six steps of instruction execution are done, and between the last step of an instruction and the first step of the next one (between store result and fetch operands) the processor checks interrupts. if none, move on, if yes, switch control to ISR (interrupt service routine), which will execute and then move on to the next fetch operands.

callee-save

the subroutine saves register contents in memory as part of its method, and restores the register contents from memory before returning.

traps

there is a table in memory that stores the starting location in memory of each trap subroutine. the trap label (GETC or TRAP x20) will specify the location in that table to be loaded into the PC. the original PC is stored in R7 so that the processor may continue to execute the program.

compiler

translates source file from high level language to assembly language

RET in lc3

will jump to whatever address is in R7. if JSR or JSRR were used to make the initial jump to the subroutine and the value in R7 was preserved during the subroutine, it should jump to the instruction directly after the method call