CS 330

Lakukan tugas rumah & ujian kamu dengan baik sekarang menggunakan Quizwiz!

12. DRAM is much costlier than SRAM.

Decimal "10" is _________ in hexadecimal. A. 1 B. A C. 0 D. FF

True

At a top level, a computer consists of CPU, memory, and I/O components.

Both sequential access and direct access involve a shared read-write mechanism

T/F A Thunderbolt compatible peripheral interface is no more complex than that of a simple USB device.

Database management systems and database applications are one area in which multicore systems can be used effectively.

T/F It is the responsibility of the processor to periodically check the status of the I/O module until it finds that the operation is complete.

T/F The disadvantage of the software poll is that it is time consuming.

T/F When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA).

The processor requires its own local memory.

data link

The purpose of the PCIe __________ layer is to ensure reliable delivery of packets across the PCIe link.

all of the above

The von Neumann architecture is based on which concept? A. data and instructions are stored in a single read-write memory B. the contents of this memory are addressable by location C. execution occurs in a sequential fashion D. all of the above

data communications

When data are moved over longer distances, to or from a remote device, the process is known as __________. A. data communications B. registering C. structuring D. data transport

False

When data are moved over longer distances, to or from a remote device, the process is known as data transport.

I/O

When data are received from or delivered to a device that is directly connected to the computer, the process is known as __________.

C. write through

When using the __________ technique all write operations made to main memory are made to the cache as well. A. write back B. LRU C. write through D. unified cache

balanced

With _________ transmission signals are transmitted as a current that travels down one conductor and returns on the other.

False

With asynchronous timing the occurrence of events on the bus is determined by a clock.

False

Workstation systems cannot support highly sophisticated engineering and scientific applications.

False

Year by year the cost of computer systems continues to rise.

Function

_________ is the operation of each individual component as part of the structure.

A. Direct mapping

__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line. A. Direct mapping B. Associative mapping C. Set associative mapping D. None of the above

External

__________ memory consists of peripheral storage devices, such as disk and tape.

Branch prediction

___________ potentially increases the amount of work available for the processor to execute. A. Branch prediction B. Performance balance C. Pipelining D. BIPS

1. Which of the following is an Intel 8085 external signal? A. CLK(OUT) B. read control C. HOLDA D. all of the above

all of the above

The ________ contains I/O protocols that are mapped on to the transport layer. A. cable B. application C. common transport D. physical

application

In the __________ mode the instruction includes a displacement to be added to a base register, which may be any of the general-purpose registers.

base with displacement

_________ format covers five floating-point representations, three binary and two decimal, whose encodings are specified by the standard, and which can be used for arithmetic.

basic

If a programmer wished to program directly in machine language it would be necessary to enter the program as ________ data.

binary

1. The _________ is a small cache memory associated with the instruction fetch stage of the pipeline. A. dynamic branch B. loop table C. branch history table D. flag

branch history table

1. Machine cycles are defined to be equivalent to ________ accesses. A. flag B. bus C. clock D. path

bus

Four bits is called a _________. A. radix point B. byte C. nibble D. binary digit

byte

Blocks of memory, recently used global variables, memory addressing, and one operand addressed and accessed per cycle are characteristics of _________ organizations.

cache

11. Instruction-level parallelism is also determined by __________which is the time until the result of an instruction is available for use as an operand in a subsequent instruction.

chip multiprocessing

1. The ________ portion of the control unit issues a repetitive sequence of pulses. A. instruction register B. flag C. control bus signals D. clock

clock

12. The timing of processor operations is synchronized by the __________ and controlled by the control unit with control signals.

clock

5. A _________ is a competition of two or more instructions for the same resource at the same time.

cluster

1. Putting rendering on one processor, AI on another, and physics on another is an example of _________ threading. A. coarse-grained B. multi-instance C. fine-grained D. hybrid

coarse-grained

A ________ is an interconnected set of gates whose output at any time is a function only of the input at that time.

combinational circuit

The ________ layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed peripheral I/O technology. A. cable B. application C. common transport D. physical

common transport

The acronym CISC stands for _________.

complex instruction set computer

1. The groupings of micro-operations must follow which rule? A. a sequence of events does not need to be followed B. use read to and write from the same register in one time unit C. conflicts must be avoided D. all of the above

conflicts must be avoided

The ________ command is used to activate a peripheral and tell it what to do. A. control B. test C. read D. write

control

4. The ____________ generated by the control unit cause the opening and closing of logic gates, resulting in the transfer of data to and from registers and the operation of the ALU.

control signals

The MIPS R4000 processor chip is partitioned into two sections, one containing the CPU and the other containing a _________ for memory management.

coprocessor

The GIC distributes interrupts to individual _________. A. dies B. cores C. QPI D. interconnects

cores

A ________ is a register whose value is easily incremented by 1 modulo the capacity of the register.

counter

1. A ________ hazard occurs when there is a conflict in the access of an operand location. A. resource B. data C. structural D. control

data

Data are exchanged with the processor from external memory through a _________.

data bus

Instruction types can be categorized as: data processing, data storage, control, and ________.

data movement

In the _________ system, 10 different digits are used to represent numbers with a base of 10.

decimal

In everyday life we use a system based on decimal digits to represent numbers, and refer to the system as the __________.

decimal system

A _________ is a combinational circuit with a number of output lines, only one of which is asserted at any time.

decoder

14. A single piece of silicon is called a ________.

die

Not common on contemporary architectures, ___________ requires only one memory reference and no special calculation, but provides only a limited address space.

direct addressing

In __________ mode the I/O module and main memory exchange data directly, without processor involvement.

direct memory access (DMA)

Two classes of events cause the x86 to suspend execution of the current instruction stream and respond to the event: interrupts and ________.

exceptions

8. In the operation of the Intel Core each instruction is translated into one or more fixed-length RISC instructions known as _________.

exclusive

1. The _________ stage includes ALU operations, cache access, and register update. A. decode B. execute C. fetch D. write back

execute

IEEE 754-2008 defines an __________ format as a format with a precision and range that are defined under user control.

extendable precision

Introduced by IBM with its System/360, the _________ is a set of computers offered with different price and performance characteristics that presents the same architecture to the user.

family concept

1. The _________ cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory. A. execute B. indirect C. fetch D. interrupt

fetch

A processor must: fetch instruction, interpret instruction, process data, write data, and _________.

fetch data

1. A loop that iterates over an array of data can be split up into a number of smaller parallel loops in individual threads that can be scheduled in parallel when using ________ threading. A. multi-process B. fine-grained C. hybrid D. coarse

fine-grained

_________ representation is when the radix point is fixed and assumed to be to the right of the rightmost digit.

fixed point

11. The key control unit inputs are: clock, instruction register, control signals from control bus, and _________.

flags

The simplest form of sequential circuit is the _________.

flip-flop

The 8237 DMA is known as a _________ DMA controller. A. command B. cycle stealing C. interrupt D. fly-by

fly-by

The fundamental building block of all digital logic circuits is the _______.

gate

The use of subnormal numbers is referred to as _________ underflow.

gradual

A combinational circuit can be defined by Boolean equations, truth table, and _________.

graphical symbols

12. The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and __________ on the same chip.

graphics processing units (GPUs)

The register contains additional bits, called __________, which are used to pad out the right end of the significand with 0s.

guard bits

13. Control unit implementation techniques fall into two categories: microprogrammed implementation and ___________ implementation.

hardwired

15. In a __________ implementation the control unit is essentially a state machine circuit and its input logic signals are transformed into a set of output logic signals, which are the control signals.

hardwired

Because 16 symbols are used, the notation is called hexadecimal and the 16 symbols are the __________.

hexadecimal

15. An alternative to _________ is a scoreboarding.

hybrid

The simplest form of addressing is __________ addressing.

immediate

Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion, out-of-order issue with out-of-order completion, and ____________.

in-order issue without out of order completion

9. If the instruction specifies an indirect address, then a(n) ________ cycle must precede the execute cycle.

indirect

C. direct access

individual blocks or records have a unique address based on physical location with __________. A. associative access B. physical access C. direct access D. sequential access

10. __________ is when the control unit examines the opcode and generates a sequence of micro-operations based on the value of the opcode.

instruction decoding

The _________ predicts the instruction stream, fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.

instruction fetch unit

A(n) __________ defines the layout of the bits of an instruction in terms of its constituent fields, must include an opcode and, implicitly or explicitly, zero or more operands.

instruction format

The term _________ parallelism refers to the degree to which, on average, the instructions of a program can be executed in parallel.

instruction level

The collection of different instructions that the processor can execute is referred to as the processor's _________.

instruction set

The ________ is a buffer used to decouple the decode and execute stages of the pipeline to allow out-of-order issue.

instruction window

__________ format is a fully specified, fixed-length binary encoding that allows data interchange between different platforms and that can be used for storage.

interchange

When the processor, main memory, and I/O share a common bus, two modes of addressing are possible: memory mapped and ________.

isolated

The most common means of computer/user interaction is a __________. A. keyboard/monitor B. mouse/printer C. modem/printer D. monitor/printer

keyboard/monitor

7. The __________ register specifies the address in memory for a read or write operation.

memory address (MAR)

8. The __________ register contains the value to be stored in memory or the last value read from memory.

memory buffer (MBR)

The actual mapping to a physical address is a function of the _________ and is invisible to the programmer.

memory management unit (MMU)

The ________ protects critical data used by the operating system from user applications, separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only, and detecting unexpected memory accesses that could potentially break the system.

memory protection unit

The ________ feature enables moving dirty data from one CPU to another without writing to L2 and reading the data back in from external memory. A. migratory lines B. DDI C. VFP unit D. IPIs

migratory lines

Opcodes are represented by abbreviations, called __________ that indicate the operation.

mnemonics

The __________ reference tells the processor where to fetch the next instruction after the execution of this instruction is complete.

next instruction

Binary digits grouped into sets of four bits are called a _________.

nibble

In the number 472.156 the 2 is the _________. A. most significant digit B. radix point C. least significant digit D. none of the above

none of the above

A __________ is one in which the most significant digit of the significand is nonzero.

normal number

With ____________ any number of instructions may be in the execution stage at any one time, up to the maximum degree of machine parallelism across all functional units.

out of order completion

If two numbers are added, and they are both positive or both negative, then _________ occurs if and only if the result has the opposite sign.

overflow

_________ occurs when an arithmetic operation results in an absolute value greater than can be expressed with an exponent of 128.

overflow

In a _________ interface there are multiple lines connecting the I/O module and the peripheral and multiple bits are transferred simultaneously.

parallel

When the divisor is able to divide the number, a 1 is placed in the quotient and the divisor is subtracted from the partial dividend; the result is referred to as a ________.

partial remainder

An external device connected to an I/O module is often referred to as a __________ device.

peripheral

The Thunderbolt protocol _________ layer is responsible for link maintenance including hot-plug detection and data encoding to provide highly efficient data transfer. A. cable B. application C. common transport D. physical

physical

A __________ occurs when the pipeline, or some portion of the pipeline, must stall because conditions do not permit continued execution.

pipeline hazard

In a __________ number system, each number is represented by a string of digits in which each digit position i has an associated weight ri, where r is the radix of the number system.

positional

The acronym RISC stands for __________.

reduced instruction set computer

Just as register addressing is analogous to direct addressing, ________ addressing is analogous to indirect addressing.

An alternative to _________ is a scoreboarding.

A _________ is a competition of two or more instructions for the same resource at the same time.

resource conflict

15. A ________ connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local area network, wide area network, or storage areanetwork. A. memory controller B. TCA C. HCA D. router

router

The acronym SPARC stands for __________.

scalable processor architecture

__________ explicitly specifies which segment register an instruction should use, overriding the default segment-register selection generated by the x86 for that instruction.

segment override

The ________ is responsible for maintaining coherency among L1 data caches. A. VFP unit B. distributed interrupt controller C. snoop control unit (SCU) D. watchdog

snoop control unit (SCU)

Sometimes referred to as a pushdown list or last-in-first-out queue, a __________ is a linear array of locations.

stack

Zero-address instructions are applicable to a special memory organizations called a _________, which is a last-in-first-out set of locations.

stack

_________ are bits in special registers that may be set by certain operations and used in conditional branch instructions.

status flags

6. _________ is a measure of the ability of the processor to take advantage of instruction-level parallelism.

time-shared bus

Each gate is defined in three ways: graphic symbol, algebraic notation, and __________.

truth table

________ can improve performance by reducing loop overhead, increasing instruction parallelism by improving pipeline performance, and improving register, data cache, or TLB locality.

unrolling

A ________ machine is an instance of an operating system along with one or more applications running in an isolated memory partition within the computer, enabling different operating systems to run in the same computer at the same time, as well as preventing applications from interfering with each other.

virtual

The _________ command causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral. A. control B. test C. read D. write

write

The three types of data hazards are: read after write (RAW), write after write (WAW), and _________.

write after read (WAR)

The most important general categories of data are: addresses, numbers, characters, and _________.

logical data

1. The _________ contains the address of an instruction to be fetched. A. instruction register B. memory address register C. memory buffer register D. program counter

program counter

Many processor designs include a register or set of registers often known as the _________ that contain status information and condition codes.

program status word (PSW)

A _________ is a relatively small PLD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable.

programmable logic array (PLA)

Also referred to as a field-programmable device (FPD), a __________ refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs.

programmable logic devide (PLD)

1. A _________ architecture is one that makes use of more, and more fine-grained pipeline stages. A. parallel B. superpipelined C. superscalar D. hybrid

superpipelined

A ________ architecture replicates each of the pipeline stages so that two or more instructions at the same stage of the pipeline can be processed simultaneously.

superscalar

A ________ implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.

superscalar

The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.

superscalar

1. The OS usually runs in ________. A. supervisor mode B. abort mode C. undefined mode D. fast interrupt mode

supervisor mode

disk

1. A __________ is a circular platter constructed of nonmagnetic material, called the substrate, coated with a magnetizable material.

C. DDR3

12. ________ increases the prefetch buffer size to 8 bits. A. CDRAM B. RDRAM C. DDR3 D. all of the above

Re-RAM

12. __________ works by creating resistance rather than directly storing charge.

B. virtual addresses

A logical cache stores data using __________. A. physical addresses B. virtual addresses C. random addresses D. none of the above

throughput

A measurement of how many tasks a computer can accomplish in a certain amount of time is called a(n) __________ . A. real-time system B. application analysis C. cycle speed D. throughput

False

A microcomputer architecture and organization relationship is not very close.

1. _________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions. A. Machine parallelism B. Instruction-level parallelism C. Output dependency D. Procedural dependency

I/O mechanisms

Architectural attributes include __________ . A. I/O mechanisms B. control signals C. interfaces D. memory technology used

In the number 3109, the 9 is referred to as the _________. A. most significant digit B. least significant digit C. radix D. base

B. least significant digit

1. The superscalar approach can be used on __________ architecture. A. RISC B. CISC C. neither RISC nor CISC D. both RISC and CISC

1. _________ determines the control and pipeline organization. A. Calculation B. Execution sequencing C. Operations performed D. Operands used

Although considered obsolete, the term _________ is sometimes used instead of significand. A. minuend B. mantissa C. base D. subtrahend

B. mantissa

Negative numbers greater than 2^-127 are called _________. A. negative overflow B. negative underflow C. positive overflow D. positive underflow

B. negative underflow

The ________ specifies the operation to be performed. A. source operand reference B. opcode C. next instruction reference D. processor register

B. opcode

The number of machine cycles for an instruction depends on the number of times the processor must communicate with internal devices.

The sequence of instruction cycles are always the same as the written sequence of instructions that make up the program.

__________ are characterized by the ability to support thousands of parallel execution threads A. CPUs B. QPIs C. GPUs D. ISAs

GPUs

7. ________ threading involves the selective use of fine-grain threading for some systems and single threading for other systems.

Hybrid

True

Interfaces between the computer and peripherals is an example of an organizational attribute.

1. The ________ is connected to the data lines of the system bus. A. MAR B. PC C. MBR D. IR

MBR

1. The _________ contains a word of data to be written to memory or the word most recently read. A. MAR B. PC C. MBR D. IR

MBR

10. The principal building block of the IBM zEnterprise EC12 mainframe is the __________ .

MCM (multichip module)

4. The term _________ parallelism refers to the degree to which on average, the instructions of a program can be executed in parallel.

MIMD.

3. ________ exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle.

MISD

Intel's ________ technology is a set of highly optimized instructions for multimedia tasks.

MMX

11. The SCU uses hybrid MESI and _________ protocols to maintain coherency between the individual L1 data caches and the L2 cache.

MOESI

__________ is a process where new inputs are accepted at one end before previously accepted inputs appear as outputs at the other end.

Pipelining

1. _________ states that performance increase is roughly proportional to square root of increase in complexity.

Pollack's rule

A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache.

A register is a digital circuit used within the CPU to store one or more bits of data.

ARM architecture has yet to implement superscalar techniques in the instruction pipeline.

ARM processors support data types of 8 (byte), 16 (halfword), and 32 (word) bits in length.

Actual floating-point representations include a special bit pattern to designate zero.

Addition and subtraction can be performed on numbers in twos complement notation by treating them as unsigned integers.

Addresses are a form of data.

Almost all RISC instructions use simple register addressing.

Although convenient for computers, the binary system is exceedingly cumbersome for human beings.

An advantage of biased representation is that non-negative floating-point numbers can be treated as integers for comparison purposes.

An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.

Any Boolean function can be implemented in electronic form as a network of gates.

At the completion of the execute cycle a test is made to determine whether any enabled interrupts have occurred, and if they have, the interrupt cycle occurs.

Both sign-magnitude representation and twos complement representation use the most significant bit as a sign bit.

Combinational circuits are often referred to as "memoryless" circuits because their output depends only on their current input and no history of prior inputs is retained.

Compared with addition and subtraction, multiplication is a complex operation, whether performed in hardware of software.

Direct data intervention enables copying clean data from one CPU L1 data cache to another CPU L1 data cache without accessing external memory.

Each micro-operation of the fetch cycle involves the movement of data into or out of a register.

Each phase of the instruction cycle can be decomposed into a sequence of elementary micro-operations.

Even if an individual application does not scale to take advantage of a large number of threads, it is still possible to gain from multicore architecture by running multiple instances of the application in parallel.

Events in the digital computer are synchronized to a clock pulse so that changes occur only when a clock pulse occurs.

For each 1 on the multiplier, an add and a shift operation are required; but for each 0 only a shift is required.

For the control unit to perform its function it must have inputs that allow it to determine the state of the system and outputs that allow it to control the behavior of the system.

Hexadecimal notation is more compact than binary notation.

In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations.

In effect, the Intel Core architecture implements a CISC instruction set architecture on a RISC microarchitecture.

In general, a decoder has n inputs and 2n outputs.

In the absence of parentheses, the AND operation takes precedence over the OR operation.

The numbers represented in floating-point notation are not spaced evenly along the number line, as are fixed-point numbers.

The operation of the digital computer is based on the storage and processing of binary data.

The operation to be performed is specified by a binary code known as the operation code.

The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle.

The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.

The principal price to pay for variable-length instructions is an increase in the complexity of the processor.

The processor needs to store instructions and data temporarily while an instruction is being executed.

The register file employs much shorter addresses than addresses for cache and memory.

The register file is on the same chip as the ALU and control unit.

The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.

The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution.

SPEC

The best-known collection of benchmark suites is defined and maintained by an industry consortium known as __________.

__________ is when the increment or decrement of the index register after each reference to it is done automatically as part of the same instruction cycle.

autoindexing

The _________ system has only two digits, 0 and 1.

binary

The _________ system uses only the numbers 0 and 1. A. positional B. binary C. hexadecimal D. decimal

binary

1. The ________ determines the opcode and the operand specifiers. A. decode instruction B. fetch operands C. calculate operands D. execute instruction

decode instruction

A very powerful mode of addressing, __________ combines the capabilities of direct addressing and register indirect addressing, requiring that the instruction have two address fields, at least one of which is explicit.

displacement addressing

The major cost in the life cycle of a system is hardware.

A. sequence acess

"Memory is organized into records and access must be made in a specific linear sequence" is a description of __________. A. sequential access B. direct access C. random access D. associative access

(2 x 10^-1) + (5 x 10^-2) + (6 x 10^-3) represents the number _________.

0.256

C. the glass substrate

1. Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write errors, are all benefits of ___________. A. magnetic read and write mechanisms B. platters C. the glass substrate D. a solid state drive

cores

1. In earlier computers the most common form of random-access storage for computer main memory employed an array of doughnut-shaped ferromagnetic loops referred to as __________.

1. Magnetic disks are the foundation of external memory on virtually all computer systems.

1. The basic element of a semiconductor memory is the memory cell.

D. all of the above

1. Which properties do all semiconductor memory cells share? A. they exhibit two stable states which can be used to represent binary 1 and 0 B. they are capable of being written into to set the state C. they are capable of being read to sense the state D. all of the above

In the decimal system, ________ different digits are used to represent numbers with a base of 10.

The decimal system has a radix of _________.

10. A number of chips can be grouped together to form a memory bank.

10. RAID is a set of physical disk drives viewed by the operating system as a single logical drive.

A. access time

10. The sum of the seek time and the rotational delay equals the _________, which is the time it takes to get into position to read or write. A. access time B. gap time C. transfer time D. constant angular velocity

rotational delay (rotational latency)

10. The time required to move the disk arm to the required track is the __________.

NAND

10. The two distinctive types of flash memory are designated as NOR and ______ .

C. DDR-DRAM

10. With __________ the data transfer is synchronized to both the rising and falling edge of the clock, rather than just the rising edge. A. CDRAM B. SDRAM C. DDR-DRAM D. RDRAM

Binary 0001 0000 0000 represents ________ in hexadecimal.

100

Decimal "10" is __________ in binary. A. 1000 B. 0010 C. 1010 D. 0001

1010

11. An error-correcting code enhances the reliability of the memory at the cost of added complexity.

11. RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve performance.

RAID

11. The _________ strategy employs multiple disk drives and distributes data in such a way as to enable simultaneous access to data from multiple drives, thereby improving I/O performance and allowing easier incremental increases in capacity.)

A. DDR2

11. __________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip. A. DDR2 B. RDRAM C. CDRAM D. DDR3

A. RAID

11. __________ is the standardized scheme for multiple-disk database design. A. RAID B. CAV C. CLV D. SSD

STT-RAM

11. ___________ is a new type of Magnetic RAM, which features non-volatility, fast writing/reading speed, and high programming endurance and zero standby power.

12. Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer rates.

B. 1

12. RAID level ________ has the highest disk overhead of all RAID types. A. 0 B. 1 C. 3 D. 5

parallel

12. RAID levels 2 and 3 make use of a _________ access technique in which all member disks participate in the execution of every I/O request.

solid state

13. A _________ drive is a memory device made with solid-state components that can be used as a replacement to a hard disk drive.

Double-data-rate SDRAM (DDR SDRAM)

13. A new version of SDRAM, referred to as __________, can send data twice per clock cycle, once on the rising edge of the clock pulse and once on the falling edge.

13. Flash memory is only used for internal memory applications.

13. The SSDs now on the market use a type of semiconductor memory referred to as flash memory.

A. 200 to 400

13. Theoretically, a DDR module can transfer data at a clock rate in the range of __________ Mbps. A. 200 to 400 B. 400 to 1066 C. 600 to 1400 D. 800 to 1600

B. 800 to 2133

14. A DDR3 module transfers data at a clock rate of __________ Mbps. A. 600 to 1200 B. 800 to 2133 C. 1000 to 2000 D. 1500 to 3000

14. SSD performance has a tendency to speed up as the device is used.

14. The SDRAM performs best when it is transferring large blocks of data sequentially such as for word processing, spreadsheets, and multimedia.

DRAM

14. The traditional __________ chip is constrained both by its internal architecture and by its interface to the processor's memory bus.

C. Constant linear velocity (CLV)

14. ________ is when the disk rotates more slowly for accesses near the outer edge than for those near the center. A. Constant angular velocity (CAV) B. Magnetoresistive C. Constant linear velocity (CLV) D. Seek time

serpentine

14. cThe typical recording technique used in serial tapes is referred to as _________ recording.

no connect (NC)

15. A typical DRAM pin configuration will include the __________ pin if necessary in order to have an even number of pins.

15. Flash memory becomes unusable after a certain number of writes

15. NOR memory is better suited for external memory such as USB flash drives and memory cards.

independent

15. RAID levels 4 through 6 make use of an __________ access technique that allows separate I/O requests to be satisfied in parallel.

A.lands

15. The areas between pits are called _________. A. lands B. sectors C. cylinders D. strips

D. PCRAM

15. __________ is a good candidate to replace or supplement DRAM for main memory. A. STT-RAM B. ReRAM C. RamBus D. PCRAM

The Intel Core i7-990X chip supports _________ forms of external communications to other chips. A. 4 B. 2 C. 6 D. 8

To convert a number from binary notation to decimal notation all that is required is to multiply each binary digit by the appropriate power of ________ and add the results.

True

A key requirement for PCIe is high capacity to support the needs of higher data rate I/O devices such as Gigabit Ethernet.

2. A characteristic of ROM is that it is volatile.

B. gaps

2. Adjacent tracks are separated by _________. A. sectors B. gaps C. pits D. heads

head

2. Data are recorded on and later retrieved from the disk via a conducting coil named the _________.

2. During a read or write operation, the head rotates while the platter beneath it stays stationary.

A. RAM

2. One distinguishing characteristic of memory that is designated as _________ is that it is possible to both read data from the memory and to write new data into the memory easily and rapidly. A. RAM B. ROM C. EPROM D. EEPROM

semiconductor

2. RAM, ROM, PROM, EPROM, EEPROM, and flash memory are all examples of __________ memory types.

dynamic

3. A _________ RAM is made with cells that store data as charge on capacitors.

C. sectors

3. Data are transferred to and from the disk in __________. A. tracks B. gaps C. sectors D. pits

tracks

3. Data is organized on the platter in a concentric set of rings called ________.

3. RAM must be provided with a constant power supply.

3. The width of a track is double that of the head.

D. all of the above

3. Which of the following memory types are nonvolatile? A. erasable PROM B. programmable ROM C. flash memory D. all of the above

All instructions in the ARM architecture are __________ bits long and follow a regular format. A. 8 B. 16 C. 32 D. 64

1. All MIPS R series processor instructions are encoded in a single ________ word format. A. 4-bit B. 8-bit C. 16-bit D. 32-bit

32-bit

static

4. A __________ RAM is a digital device that uses the same logic elements used in the processor.

B. SRAM

4. In a _________, binary values are stored using traditional flip-flop logic-gate configurations. A. ROM B. SRAM C. DRAM D. RAM

D. 512

4. In most contemporary systems fixed-length sectors are used, with _________ bytes being the nearly universal sector size. A. 64 B. 128 C. 256 D. 512

4. The two traditional forms of RAM used in computers are DRAM and SRAM.

4. There are typically hundreds of sectors per track and they may be either fixed or variable lengths.

multiple zone recording

4. To increase density in a straightforward CAV system, modern hard disk systems use a technique known as __________, in which the surface is divided into a number of concentric zones.

Binary 0101 is hexadecimal _________. A. 0 B. 5 C. A D. 10

C. double sided

8. When the magnetizable coating is applied to both sides of the platter the disk is then referred to as _________. A. multiple sided B. substrate C. double sided D. all of the above

A. Soft errors

8. _________ can be caused by power supply problems or alpha particles. A. Soft errors B. AGT errors C. Hard errors D. SEC errors

C. ROM

5. A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it. A. RAM B. SRAM C. ROM D. flash memory

5. A bit near the center of a rotating disk travels past a fixed point slower than a bit on the outside.

5. A static RAM will hold its data as long as power is supplied to it.

fixed-head

5. In a _________ disk there is one read-write head per track and all of the heads are mounted on a rigid arm that extends across all trac

A. constant angular velocity

5. Scanning information at the same rate by rotating the disk at a fixed speed is known as the _________. A. constant angular velocity B. magnetoresistive C. rotational delay D. constant linear velocity

flash memory

5. Three common forms of read-mostly memory are: EPROM, EEPROM, and _________.

hard

6. A __________ failure is a permanent physical defect so that the memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1.

movable-head

6. In a __________ disk there is only one read-write head mounted on an arm that can be extended or retracted to be able to be positioned above any track.

6. Nonvolatile means that power must be continuously supplied to the memory to preserve the bit values.

B. CAV

6. The disadvantage of _________ is that the amount of data that can be stored on the long outer tracks is only the same as what can be stored on the short inner tracks. A. SSD B. CAV C. ROM D. CLV

6. The disadvantage of using CAV is that individual blocks of data can only be directly addressed by track and sector.

A. flash memory

6. With _________ the microchip is organized so that a section of memory cells are erased in a single action. A. flash memory B. SDRAM C. DRAM D. EEPROM

1. The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU. A. 16 B. 32 C. 64 D. 128

1. The ARM architecture supports _______ execution modes. A. 2 B. 8 C. 11 D. 7

A. nonremovable

7. A __________ disk is permanently mounted in the disk drive, such as the hard disk in a personal computer. A. nonremovable B. movable-head C. double sided D. removable

soft

7. A __________ error is a random, nondestructive event that alters the contents of one or more memory cells without damaging the memory.

7. A removable disk can be removed and replaced with another disk.

floppy

7. The _________ disk is a small, flexible platter and the least expensive type of disk.

7. The advantage of RAM is that the data or program is permanently in main memory and need never be loaded from a secondary storage device.

B. Hard errors

7. __________ can be caused by harsh environmental abuse, manufacturing defects, and wear. A. SEC errors B. Hard errors C. Syndrome errors D. Soft errors

The most important floating-point representation is defined in IEEE Standard _________, adopted in 1985 and revised in 2008.

754

8. Semiconductor memory comes in packaged chips.

8. The head must generate or sense an electromagnetic field of sufficient magnitude to write and read properly.

Hamming

8. The simplest of the error-correcting codes is the _________ code.

Winchester

8. __________ heads are used in sealed drive assemblies that are almost free of contaminants and the head is actually an aerodynamic foil that rests lightly on the platter's surface when the disk is motionless.

The ________ is a single-chip, general-purpose I/O module designed for use with the Intel 80386 processor.

82C55A

In the decimal system, _________ is the maximum value that a position can hold before it flips over into the next higher position.

9. All DRAMs require a refresh operation.

seek time

9. On a movable-head system, the time it takes to position the head at the track is known as __________.

synchronous

9. One of the most widely used forms of DRAM is the _________ DRAM.

B. SDRAM

9. The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. A. DDR-DRAM B. SDRAM C. CDRAM D. none of the above

D. cylinder

9. The set of all the tracks in the same relative position on the platter is referred to as a _________. A. floppy disk B. single-sided disk C. sector D. cylinder

9. The transfer time to or from the disk does not depend on the rotation speed of the disk.

1. A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions. A. delayed load B. delayed program C. delayed slot D. delayed register

1. Instead of the first instruction producing a value that the second instruction uses, with ___________ the second instruction destroys a value that the first instruction uses. A. in-order issue B. resource conflict C. antidependency D. out-of-order completion

1. The Patterson study examined the dynamic behavior of _________ programs, independent of the underlying architecture. A. HLL B. RISC C. CISC D. all of the above

1. The R4000 can have as many as _______ instructions in the pipeline at the same time. A. 8 B. 10 C. 5 D. 3

1. The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage. A. write back B. tag check C. data cache D. instruction execute

1. The __________ module handles multiple levels of interrupt signals. A. interrupt control B. incrementer address latch C. serial I/O control D. decrementer address latch

1. The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________. A. true data dependency B. output dependency C. procedural dependency D. antidependency

1. Utilizing a branch target buffer (BTB), the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions. A. 486 B. Pentium C. Intel Core D. Pentium Pro

1. With _______, register banks are replicated so that multiple threads can share the use of pipeline resources. A. SMT B. pipelining C. scalar D. superscalar

1. ________ indicates whether this micro-op is scheduled for execution, has been dispatched for execution, or has completed execution and is ready for retirement. A. State B. Memory address C. Micro-op D. Alias register

1. ________ is a protocol used to issue instructions. A. Micro-ops B. Scalar C. SIMD D. Instruction issue policy

1. ________ refers to the process of initiating instruction execution in the processor's functional units. A. Instruction issue B. In-order issue C. Out-of-order issue D. Procedural issue

1. _________ instructions are used to position quantities in registers temporarily for computational operations. A. Load-and-store B. Window C. Complex D. Branch

1. __________ are the functional, or atomic, operations of a processor. A. Micro-operations B. Interrupts C. Subcycles D. All of the above

1. ___________ states that performance increase is roughly proportional to square root of increase in complexity. A. Pollack's Rule B. Moore's Law C. Amdahl's Law D. MOESI Rule

C. tag

A line includes a _________ that identifies which particular block is currently being stored. A. cache B. hit C. tag D. locality

I/O

A _________ interrupt simply means that the processor can and will ignore that interrupt request signal.

D. Blu-ray DVD

A _________ is a high-definition video disk that can store 25 Gbytes on a single layer on a single side. A. DVD B. DVD-R C. DVD-RW D. Blu-ray DVD

system interconnection

A _________ is a mechanism that provides for communication among CPU, main memory, and I/O. A. system interconnection B. CPU interconnection C. peripheral D. processor

memory buffer

A _________ register contains the data to be written into memory or receives the data read from memory.

benchmark

A _________ suite is a collection of programs, defined in a high-level language, that together attempt to provide a representative test of a computer in a particular application or system programming area.

microprogrammed

A __________ control unit operates by executing micro-instructions that define the functionality of the control unit.

bus

A __________ is a communication pathway connecting two or more devices.

GPU

A __________ is a core designed to perform parallel operations on graphics data. A. MIC B. ALU C. GPU D. PGD

protocol

A __________ is the high-level set of rules for exchanging packets of data between devices. A. bus B. protocol C. packet D. QPI

memory address

A __________ register specifies the address in memory for the next read or write.

hierarchical

A __________ system is a set of interrelated subsystems. A. secondary B. hierarchical C. complex D. functional

system bus

A bus that connects major computer components (processor, memory, I/O) is called a __________. A. system bus B. address bus C. data bus D. control bus

system bus

A common example of system interconnection is by means of a ________, consisting of a number of conducting wires to which all the other components attach.

system bus

A common example of system interconnection is by means of a __________. A. register B. system bus C. data transport D. control device

True

A common measure of performance for a processor is the rate at which instructions are executed, expressed as millions of instructions per second (MIPS).

False

A key characteristic of a bus is that it is not a shared transmission medium.

True

A computer is a complex system.

True

A computer must be able to process, store, move, and control data.

False

A computer organization does not need to be designed to implement a particular architectural specification.

True

A particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology.

A. disk cache

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________. A. disk cache B. latency C. virtual address D. miss

software

A sequence of codes or instructions is called __________. A. software B. memory C. an interconnect D. a register

False

A straight comparison of clock speeds on different processors tells the whole story about performance.

A typical computer system is equipped with a hierarchy of memory subsystems, some internal to the system and some external

diasabled

A(n) ________ interrupt is generated by an I/O controller to signal normal completion of an operation, request service from the processor, or to signal a variety of error conditions.

timer

A(n) _________ interrupt is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis.

hardware failure interrupt

A(n) _________ is generated by a failure such as power failure or memory parity error. A. I/O interrupt B. hardware failure interrupt C. timer interrupt D. program interrupt

program interrupt

A(n) _________ is generated by some condition that occurs as a result of an instruction execution. A. timer interrupt B. I/O interrupt C. program interrupt D. hardware failure interrupt

Arithmetic

A(n) __________ Mean is a good candidate for comparing the execution time performance of several systems. A. Composite in B. Arithmetic C. Harmonic D. Evaluation

The binary string 110111100001 is equivalent to __________. A. DE116 B. C7816 C. FF6416 D. B8F16

A. DE116

_______ instructions are needed to transfer programs and data into memory and the results of computations back out to the user. A. I/O B. Transfer C. Control D. Branch

A. I/O

__________ has the advantage of large address space, however it has the disadvantage of multiple memory references. A. Indirect addressing B. Direct addressing C. Immediate addressing D. Stack addressing

A. Indirect addressing

The ________ flip-flop has two inputs and all possible combinations of input values are valid. A. J-K B. D C. S-R D. clocked S-R

A. J-K

________ instructions operate on the bits of a word as bits rather than as numbers, providing capabilities for processing any other type of data the user may wish to employ. A. Logic B. Arithmetic C. Memory D. Test

A. Logic

________ are used in digital circuits to control signal and data routing. A. Multiplexers B. Program counters C. Flip-flops D. Gates

A. Multiplexers

________ is when the result may be larger than can be held in the word size being used. A. Overflow B. Arithmetic shift C. Underflow D. Partial product

A. Overflow

The __________ byte consists of three fields: the Scale field, the Index field and the Base field. A. SIB B. VAX C. PDP-11 D. ModR/M

A. SIB

Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract instructions, and test and compare instructions? A. data-processing instructions B. branch instructions C. load and store instructions D. extend instructions

A. data-processing instructions

The _________ table provides the value of the next output when the inputs and the present output are known, which is exactly the information needed to design the counter or any sequential circuit. A. excitation B. Kenough C. J-K flip-flop D. FPGA

A. excitation

A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals. A. gate B. decoder C. counter D. flip-flop

A. gate

For the _________ mode, the operand is included in the instruction. A. immediate B. base C. register D. displacement

A. immediate

For _________, the address field references a main memory address and the referenced register contains a positive displacement from that address. A. indexing B. base-register addressing C. relative addressing D. all of the above

A. indexing

In the number 3109, the 3 is referred to as the _________. A. most significant digit B. least significant digit C. radix D. base

A. most significant digit

Positive numbers less than 2^-127 are called ________. A. positive underflow B. positive overflow C. negative underflow D. negative overflow

A. positive underflow

Moving the sign bit to the new leftmost position and filling in with copies of the sign bit is called _________. A. sign extension B. range extension C. bit extension D. partial extension

A. sign extension

The _________ instruction includes an implied address. A. skip B. rotate C. stack D. push

A. skip

CPUs make use of _________ counters, in which all of the flip-flops of the counter change at the same time. A. synchronous B. asynchronous C. clocked S-R D. timed ripple

A. synchronous

1. The ________ pulse signals the start of each machine cycle from the control unit and alerts external circuits. A. AC B. INSTR C. ALE D. OUT

ALE

The U.S. national version of the International Reference Alphabet is referred to as __________.

ASCII

Today the most commonly used character code is the IRA, referred to in the United States as _____________.

ASCII

All of the Pentium processors include two on-chip L1 caches, one for data and one for instructions

1. _________ is a pipeline hazard. A. Control B. Resource C. Data D. All of the above

All of the above

2. _______ law assumes a program in which a fraction (1- f )of the execution time involves code that is inherently serial and a fraction f that involves code that is infinitely parallelizable with no scheduling overhead.

Amdahl's

peripheral

An I/O device is referred to as a __________. A. CPU B. control device C. peripheral D. register

False

An I/O module cannot exchange data directly with the processor.

more rapidly

An increase in clock rate means that individual operations are executed _____. A. the same B. slower C. with very little change D. more rapidly

The _________ is that part of the computer that actually performs arithmetic and logical operations on data.

Arithmetic and Logic Unit (ALU)

Hertz

At the most fundamental level, the speed of a processor is dictated by the pulse frequency produced by the clock, measured in cycles per second, or_________.

1. A ________ instruction can be used to account for data and branch delays. A. SUB B. NOOP C. JUMP D. all of the above

1. Each instruction executed during an instruction cycle is made up of shorter ______. A. executions B. subcycles C. steps D. none of the above

1. One way to control power density is to use more of the chip area for ________. A. multicore B. cache memory C. silicon D. resistors

1. The ________ introduced a full-blown superscalar design with out-of-order execution. A. Pentium B. Pentium Pro C. 386 D. 486

1. The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed. A. resource dependency B. procedural dependency C. output dependency D. true data dependency

T/F With isolated I/O there is a single address space for memory locations and I/O devices.

1. _________ is when multiple pipelines are constructed by replicating execution resources, enabling parallel execution of instructions in parallel pipelines so long as hazards are avoided. A. Vectoring B. Superscalar C. Hybrid multithreading D. Pipelining

1. __________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping. A. Flow dependency B. Instruction-level parallelism C. Machine parallelism D. Instruction issue

The decimal system has a base of _________. A. 0 B. 10 C. 100 D. 1000

B. 10

Which digit represents "hundreds" in the number 8732? A. 8 B. 7 C. 3 D. 2

B. 7

__________ has the advantage of flexibility, but the disadvantage of complexity. A. Stack addressing B. Displacement addressing C. Direct addressing D. Register addressing

B. Displacement addressing

A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs. A. SPLD B. FPGA C. PAL D. PLA

B. FPGA

The "read word from memory" and "increment PC" actions cannot be used simultaneously because they will interfere with each other.

The unary operation _________ inverts the value of its operand. A. OR B. NOT C. NAND D. XOR

B. NOT

_________ is a principle by which two variables are independent of each other. A. Opcode B. Orthogonality C. Completeness D. Autoindexing

B. Orthogonality

For more than four variables an alternative approach is a tabular technique referred to as the _________ method. A. DeMorgan B. Quine-McCluskey C. Karnaugh map D. Boole-Shannon

B. Quine-McCluskey

__________ representation is almost universally used as the processor representation for integers. A. Biased B. Twos compliment C. Sign-magnitude D. Decimal

B. Twos compliment

The most fundamental type of machine instruction is the _________ instruction. A. conversion B. data transfer C. arithmetic D. logical

B. data transfer

A(n) _________ expresses operations in a concise algebraic form using variables. A. opcode B. high-level language C. machine language D. register

B. high-level language

The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand. A. direct addressing B. immediate addressing C. register addressing D. stack addressing

B. immediate addressing

Positive numbers greater than (2 - 2^-23) x 2^-128 are called _________. A. negative underflow B. positive overflow C. positive underflow D. negative overflow

B. positive overflow

A _________ accepts and/or transfers information serially. A. S-R latch B. shift register C. FPGA D. parallel register

B. shift register

The entire set of parameters, including return address, which is stored for a procedure invocation is referred to as a _________. A. branch B. stack frame C. pop D. push

B. stack frame

A branch instruction in which the branch is always taken is _________. A. conditional branch B. unconditional branch C. jump D. bi-endian

B. unconditional branch

The address of the next instruction to be fetched must be a real address, not a virtual address.

True

Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage of advances in device performance.

The digital circuitry in digital computers and other digital systems is designed, and its behavior is analyzed, with the use of a mathematical discipline known as __________.

Boolean Algebra

True

Both the structure and functioning of a computer are, in essence, simple.

True

Branch prediction potentially increases the amount of work available for the processor to execute.

1. SPARC refers to an architecture defined by ________. A. Microsoft B. Apple C. Sun Microsystems D. IBM

1. The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines. A. scalar B. branch C. superscalar D. flow dependency

1. The instruction location immediately following the delayed branch is referred to as the ________. A. delay load B. delay file C. delay slot D. delay register

1. _______ applications embrace threading in a fundamental way. A. Multi-instance B. Multi-process C. Java D. Threaded

1. ________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles. A. In-order completion B. In-order issue C. Out-of-order completion D. Out-of-order issue

1. ________ refers to the process of initiating instruction execution in the processor's functional units. A. Instruction issue B. In-order issue C. Out-of-order issue D. Procedural issue

1. _________ is the fastest available storage device. A. Main memory B. Cache C. Register storage D. HLL

1. _________ is where individual instructions are executed through a pipeline of stages so that while one instruction is executing in one stage of the pipeline, another instruction is executing in another stage of the pipeline. A. Superscalar B. Scalar C. Pipelining D. Simultaneous multithreading

The decimal system has a radix of 100.

Which of the following is correct? A. 25 = (2 x 102) + (5 x 101) B. 289 = (2 x 103) + (8 x 101) + (9 x 100) C. 7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100) D. 0.628 = (6 x 10-3) + (2 x 10-2) + (8 x 10-1)

C. 7523 = (7 x 103) + (5 x 102) + (2 x 101) + (3 x 100)

The operand ________ yields true if and only if both of its operands are true. A. XOR B. OR C. AND D. NOT

C. AND

The demand on power requirements has not grown as chip density and clock frequency have risen.

__________ involves the generation of partial products, one for each digit in the multiplier, which are then summed to produce the final product. A. Addition B. Subtraction C. Multiplication D. Division

C. Multiplication

The _________ was designed to provide a powerful and flexible instruction set within the constraints of a 16-bit minicomputer. A. PDP-1 B. PDP-8 C. PDP-11 D. PDP-10

C. PDP-11

________ is implemented with combinational circuits. A. Nano memory B. Random access memory C. Read only memory D. No memory

C. Read only memory

Numbers in the binary system are represented to the _________. A. base 0 B. base 1 C. base 2 D. base 10

C. base 2

Counters can be designated as _________. A. asynchronous B. synchronous C. both asynchronous and synchronous D. neither asynchronous or synchronous

C. both asynchronous and synchronous

The x86 data type that is a signed binary value contained in a byte, word, or doubleword, using twos complement representation is _________. A. general B. ordinal C. integer D. packed BCD

C. integer

In the ARM architecture only _________ instructions access memory locations. A. data processing B. status register access C. load and store D. branch

C. load and store

There must be ________ instructions for moving data between memory and the registers. A. branch B. logic C. memory D. I/O

C. memory

Indexing performed after the indirection is __________. A. relative addressing B. autoindexing C. postindexing D. preindexing

C. postindexing

The advantages of _________ addressing are that only a small address field is needed in the instruction and no time-consuming memory references are required. A. direct B. indirect C. register D. displacement

C. register

The most common scheme in implementing the integer portion of the ALU is: A. sign-magnitude representation B. biased representation C. twos complement representation D. ones complement representation

C. twos complement representation

Organizational

Control signals, interfaces between the computer and peripherals, and the memory technology used are all examples of _________ attributes.

Cache design for HPC is the same as that for other hardware platforms and applications.

Cache is not a form of internal memory

False

Changes in computer technology are finally slowing down.

True

Changes in technology not only influence organization but also result in the introduction of more powerful and more complex architectures.

The execute cycle is simple and predictable.

True

Cloud service providers use massive high-performance banks of servers to satisfy high-volume, high-transaction- rate applications for a broad spectrum of clients.

9. Individual modules called systems are assigned to individual processors with ________ threading.

Coarse-grained

architecture

Computer _________ refers to those attributes that have a direct impact on the logical execution of a program. A. organization B. specifics C. design D. architecture

False

Computer organization refers to attributes of a system visible to the programmer.

True

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

rapid

Computer technology is changing at a __________ pace. A. slow B. slow to medium C. rapid D. non-existent

1. __________ are bits set by the processor hardware as the result of operations. A. MIPS B. Condition codes C. Stacks D. PSWs

Condition codes

__________ registers are used by the control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs.

Control and status

________ instructions are those that change the format or operate on the format of data.

Conversion

________ is when the DMA module must force the processor to suspend operation temporarily. A. Interrupt B. Thunderbolt C. Cycle stealing D. Lock down

Cycle stealing

1. A single micro-operation generally involves which of the following? A. a transfer between registers B. a transfer between a register and an external bus C. a transfer between a register and the ALU D. all of the above

1. The first commercial RISC product was _________. A. SPARC B. CISC C. VAX D. the Pyramid

1. The superscalar approach can be used on __________ architecture. A. RISC B. CISC C. neither RISC nor CISC D. both RISC and CISC

1. Which of the following is a fundamental limitation to parallelism with which the system must cope? A. procedural dependency B. resource conflicts C. antidependency D. all of the above

1. Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance? A. duplication of resources B. out-of-order issue C. renaming D. all of the above

1. Which stage is required for load and store operations? A. I B. E C. D D. all of the above

1. ________ is a protocol used to issue instructions. A. Micro-ops B. Scalar C. SIMD D. Instruction issue policy

1. __________ applications are characterized by the presence of many single-threaded processes. A. Java B. Multithreaded native C. Multi-instance D. Multiprocess

Hexadecimal has a base of _________. A. 2 B. 8 C. 10 D. 16

D. 16

__________ is a design principle employed in designing the PDP-10 instruction set. A. Orthogonality B. Completeness C. Direct addressing D. All of the above

D. All of the above

_________ instructions provide computational capabilities for processing number data. A. Boolean B. Logic C. Memory D. Arithmetic

D. Arithmetic

The operation _________ yields true if either or both of its operands are true. A. NOT B. AND C. NAND D. OR

D. OR

The generic timer handles interrupt detection and interrupt prioritization.

Which data type is defined in MMX? A. packed byte B. packed word C. packed doubleword D. all of the above

D. all of the above

Which of the following interrelated factors go into determining the use of the addressing bits? A. number of operands B. number of register sets C. address range D. all of the above

D. all of the above

Which of the following is a functionally complete set? A. AND, NOT B. NOR C. AND, OR, NOT D. all of the above

D. all of the above

Which of the following is a true statement? A. a procedure can be called from more than one location B. a procedure call can appear in a procedure C. each procedure call is matched by a return in the called program D. all of the above

D. all of the above

The principal advantage of ___________ addressing is that it is a very simple form of addressing. A. displacement B. register C. stack D. direct

D. direct

The ________ exists in one of two states and, in the absence of input, remains in that state. A. assert B. complex PLD C. decoder D. flip-flop

D. flip-flop

The only form of addressing for branch instructions is _________ addressing. A. register B. relative C. base D. immediate

D. immediate

Negative numbers less than -(2 - 2^-23) x 2^128 are called _________. A. positive underflow B. positive overflow C. negative underflow D. negative overflow

D. negative overflow

In ________ representation the rule for forming the negation of an integer is to invert the sign bit. A. ones complement B. twos complement C. biased D. sign-magnitude

D. sign-magnitude

1. ________ registers may be used only to hold data and cannot be employed in the calculation of an operand address. A. General purpose B. Data C. Address D. Condition code

Data

__________ is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.

Delayed branch

True

Designers wrestle with the challenge of balancing processor performance with that of main memory and other computer components.

__________ is when a positive exponent exceeds the maximum possible exponent value. A. Significand underflow B. Significand overflow C. Exponent overflow D. Exponent underflow

Exponent overflow

10. ________ is a digital display interface standard now widely adopted for computer monitors, laptop displays, and other graphics and video interfaces. A. DisplayPort B. PCI Express C. Thunderbolt D. InfiniBand

DisplayPort

lane

Each data path consists of a pair of wires (referred to as a __________ ) that transmits data one bit at a time. A. lane B. path C. line D. bus

__________ means that the number is too small to be represented and it may be reported as 0. A. Negative underflow B. Exponent underflow C. Positive underflow D. Significand underflow

Exponent underflow

_________ formats extend a supported basic format by providing additional bits in the exponent and in the significand. A. Arithmetic B. Basic C. Extended precision D. Interchange

Extended precision

External memory is often equated with main memory

secondary

External, nonvolatile memory is referred to as ___________ or auxiliary memory

13. An interrupt is generated from software and it is provoked by the execution of an instruction.

2. The control unit (CU) does the actual computation or processing of data.

5. The allocation of control information between registers and memory are not considered to be a key design issue.

8. A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.

A Boolean function can be realized in the sum of products (SOP) form but not in the product of sums (POS) form.

A high-level language expresses operations in a basic form involving the movement of data to or from registers.

A nibble is a grouping of four decimal digits.

A number cannot be converted from binary notation to decimal notation.

A sequence of hexadecimal digits can be thought of as representing an integer in base 10.

ARM architecture has yet to implement superscalar techniques in the instruction pipeline.

As chip transistor density has increased, the percentage of chip area devoted to memory has decreased.

Because of the inherent binary nature of digital computer components, all forms of data within computers are represented by various binary codes.

Binary addition is exactly the same as Boolean algebra.

Booth's algorithm performs more additions and subtractions than a straightforward algorithm.

Cache memory is a much faster memory than the register file.

Claude Shannon, a research assistant in the Electrical Engineering Department at M.I.T., proposed the basic principles of Boolean algebra.

For addresses that reference memory the range of addresses that can be referenced is not related to the number of address bits.

For base 2 representation, a normal number is one in which the most significant bit of the significand is zero.

Hexadecimal notation is only used for representing integers.

In a system without virtual memory, the effective address is a virtual address or a register.

In any number, the rightmost digit is referred to as the most significant digit.

In effect, the Intel Core architecture implements a CISC instruction set architecture on a RISC microarchitecture.

In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.

In-order completion requires more complex instruction issue logic than out-of-order completion.

It is not necessary for the ALU to signal when overflow occurs.

Knowing the machine instruction set does not play a part in knowing the functions that the processor must perform.

Logical functions are implemented by the interconnection of decoders.

Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.

Memory references are faster than register references.

Not all machine languages include numeric data types.

Our primary counting system is based on binary digits to represent numbers.

Overflow can only occur if there is a carry.

Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0.

Procedure calls and returns are not important aspects of HLL programs.

Procedures do not allow programming tasks to be subdivided into smaller units.

T/F A multipoint external interface provides a dedicated line between the I/O module and the external device.

T/F I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.

T/F The rotating interrupt mode allows the processor to inhibit interrupts from certain devices.

T/F With a daisy chain the processor just picks the interrupt line with the highest priority.

The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in-order issue) and to write results in that same order (in-order completion).

The superscalar approach depends on the ability to execute multiple instructions in parallel.

Three of the most common uses of stack addressing are relative addressing, base-register addressing, and indexing.

Typically an instruction set will include both preindexing and postindexing.

When using graph coloring, nodes that share the same color cannot be assigned to the same register.

With hybrid threading each major module is single threaded and the principal coordination involves synchronizing all the threads with a timeline thread.

8. ________ threading is when many similar or identical tasks are spread across multiple processors.

Fine-grained

B. unit of transfer

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module. A. access time B. unit of transfer C. capacity D. memory ratio

D. access time

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use. A. memory cycle time B. direct access C. transfer rate D. access time

Tag

For set-associative mapping the cache control logic interprets a memory address as three fields: Set, Word, and __________.

performance

From a user's point of view the two most important characteristics of memory are capacity and _____________.

False

Historically the distinction between architecture and organization has not been an important one.

An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the processor, is usually referred to as an _________. A. I/O channel B. I/O command C. I/O controller D. device controller

I/O channel

An I/O module that is quite primitive and requires detailed control is usually referred to as an _________. A. I/O command B. I/O controller C. I/O channel D. I/O processor

I/O controller

Interface to the processor and memory via the system bus or central switch and interface to one or more peripheral devices by tailored data links are two major functions of an _____________.

I/O module

The _________ contains logic for performing a communication function between the peripheral and the bus. A. I/O channel B. I/O module C. I/O processor D. I/O command

I/O module

1. The _______ designates the state of the processor in terms of which portion of the cycle it is in. A. ICC B. BSA C. ALE D. ISC

ICC

1. The _________ holds the last instruction fetched. A. PC B. MBR C. MAR D. IR

__________ or fetch overlap is where, while the second stage is executing the instruction, the first stage takes advantage of any unused memory cycles to fetch and buffer the next instruction.

Instruction prefetch

1. The _________ is an example of splitting off a separate, shared L3 cache, with dedicated L1 and L2 caches for each core processor. A. IBM 370 B. ARM11 MPCore C. AMD Opteron D. Intel Core i7

Intel Core i7

In a volatile memory, information decays naturally or is lost when electrical power is switched off.

True

In general, the more devices attached to the bus, the greater the bus length and hence the greater the propagation delay.

A. miss

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory. A. miss B. hit C. line D. tag

________ enables servers, remote storage, and other network devices to be attached in a central fabric of switches and links, connecting up to 64,000 servers, storage systems, and networking devices.

InfiniBand

12. Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion out-of-order issue with out-of-order completion, and ____________.

Interleaved multithreaded scalar

C. Bytes

Internal memory capacity is typically expressed in terms of _________. A. hertz B. nanos C. bytes D. LOR

False

Interrupts do not improve processing efficiency.

It has become possible to have a cache on the same chip as the processor

architectural

It is a(n) _________ design issue whether a computer will have a multiply instruction. A. architectural B. memory C. elementary D. organizational

organizational

It is a(n) _________ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system. A. architectural B. memory C. mechanical D. organizational

1. The _________ is connected to the address lines of the system bus. A. MBR B. MAR C. PC D. IR

MAR

False

It is not possible to connect I/O controllers directly onto the system bus.

5. ________ is a multithreaded process that provides scheduling and memory management for Java applications.

Java Virtual Machine

Consisting of an array of 2" squares representing all possible combinations of values of n binary variables, the _________ is a convenient way of representing a Boolean function of a small number (up to four) of variables.

Karnaugh map

_________ is a measure of the ability of the processor to take advantage of instruction-level parallelism.

Machine parallelism

False

Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors.

The _________ byte specifies whether an operand is in a register or in memory, and if it is in memory, then fields within the byte specify the addressing mode to be used.

ModR/M

superscalar execution

Multiple parallel pipelines are used in __________ . A. speculative execution B. data flow analysis C. superscalar execution D. branch prediction

4. _________ applications are characterized by the presence of many single-threaded processes.

Multiprocess

3. __________ applications are characterized by having a small number of highly threaded processes.

Multithreaded native

The basic logical operations of Boolean algebra are AND, OR, and ________.

NOT

14. The ________ is a buffer used to decouple the decode and execute stages of the pipeline to allow out-of-order issue.

NUMA

A number with both an integer and fractional part has digits raised to both positive and negative powers of 10.

No single technology is optimal in satisfying the memory requirements for a computer system.

1. The ________ holds the address of the next instruction to be fetched. A. IR B. PC C. MAR D. MBR

CPU

Often referred to as processor the ________ controls the operation of the computer and performs its data processing functions.

One byte equals __________ bits.

clock cycle

One increment, or pulse, of a clock is referred to as a __________ . A. clock cycle B. clock rate C. clock speed D. cycle time

True

Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by a system clock.

True

Processors are so inexpensive that we now have microprocessors we throw away.

True

Program execution consists of repeating the process of instruction fetch and instruction execution.

15. The _________ is a cache-coherent, point-to-point link based electrical interconnect specification for Intel processors and chipsets that enable high-speed communications among connected processor chips.

QPI (Quick Path Interconnect)

The x86 provides four instructions to support procedure call/return: CALL, ENTER, LEAVE, and _________.

RETURN

A large number of general-purpose registers, and/or the use of compiler technology to optimize register usage, a limited and simple instruction set, and an emphasis on optimizing the instruction pipeline are all key elements of _________ architectures.

RISC (reduced instruction set computer)

False

Raw speed is far more important than how a processor performs when executing a given application.

1. __________ are a set of storage locations. A. Processors B. PSWs C. Registers D. Control units

Registers

2. The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.

SIMD

1. A ________ implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.

SISD

Secondary memory is used to store program and data files and is usually visible to the programmer only in terms of individual bytes or words.

7. Committing or _________ the instruction is when instructions are conceptually put back into sequential order and their results are recorded.

Snoopy

6. _______ is an animation engine used by Valve for its games and licensed for other game developers.

Source

9. One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.

A branch can be either forward or backward.

A combinational circuit consists of n binary inputs and m binary outputs.

_________ are included in IEEE 754 to handle cases of exponent underflow. A. Subnormal numbers B. Guard bits C. Normal numbers D. Radix points

Subnormal numbers

A cycle is made up of a sequence of micro-operations.

________ exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle.

Super pipelining

False

Superscalar execution is the same principle as seen in an assembly line.

_________ instructions are those that can be executed only while the processor is in a certain privileged state or is executing a program in a special privileged area of memory.

System control

"Don't care" conditions are when certain combinations of values of variables never occur, and therefore the corresponding output never occurs.

10. The predict-never-taken approach is the most popular of all the branch prediction methods.

11. It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.

12. Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.

14. While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur.

15. The exception modes have full access to system resources and can change modes freely.

3. Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy.

4. Condition codes facilitate multiway branches.

6. Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.

7. The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline.

In the scalar organization there are multiple functional units, each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.

In-order completion requires more complex instruction issue logic than out-of-order completion.

It has become common practice to use a symbolic representation of machine instructions.

It is common for programs, both system and application, to continue to exhibit new bugs after years of operation.

It is extremely easy to convert between binary and hexadecimal notation.

Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.

Most machines provide the basic arithmetic operations of add, subtract, multiply, and divide.

Negative powers of 10 are used to represent the positions of the numbers for decimal fractions.

One advantage of linking the addressing mode to the operand rather than the opcode is that any addressing mode can be used with any opcode.

One boundary where the computer designer and the computer programmer can view the same machine is the machine instruction set.

One drawback of sign-magnitude representation is that there are two representations of 0.

One of the trade-offs of floating-point math is that many calculations produce results that are not exact and have to be rounded to the nearest value that the notation can represent.

One of the traditional ways of describing processor architecture is in terms of the number of addresses contained in each instruction.

One technique for implementing a control unit is referred to as hardwired implementation, in which the control unit is essentially a state machine circuit.

Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program.

RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.

Register addressing is similar to direct addressing with the only difference being that the address field refers to a register rather than a main memory address.

Resources include: memories, caches, buses, and register-file ports.

T/F A disadvantage of memory-mapped I/O is that valuable memory address space is used up.

T/F A set of I/O modules is a key element of a computer system.

T/F An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations.

T/F An I/O module must recognize one unique address for each peripheral it controls.

T/F Because the 82C55A is programmable via the control register, it can be used to control a variety of simple peripheral devices.

T/F Bus arbitration makes use of vectored interrupts.

The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches.

The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems

The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones, set-top boxes, gaming consoles and automotives navigation/entertainment systems.

The base with index and displacement mode sums the contents of the base register, the index register, and a displacement to form the effective address.

The big.Little architecture uses a combination of ARM Cortex-A7 and Cortex A-15 cores.

The cache is capable of handling global as well as local variables.

The control unit controls the internal flow of data.

The control unit is the engine that runs the entire computer.

The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9.

The delay by the propagation time of signals through the gate is known as the gate delay.

The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address field.

The execution of a program consists of the sequential execution of instructions.

The focus of MMX technology is multimedia programming.

The increasingly difficult engineering challenge related to processor logic is one of the reasons that an increasing fraction of the processor chip is devote to the simpler memory logic.

The instruction set is the programmer's means of controlling the processor.

The memory transfer rate has not kept up with increases in processor speed.

The method of calculating the EA is the same for both base-register addressing and indexing.

The superscalar approach depends on the ability to execute multiple instructions in parallel.

The superscalar approach has now become the standard method for implementing high-performance microprocessors.

The use of common data paths simplifies the interconnection layout and the control of the processor.

The value of the mode field determines which addressing mode is to be used.

The value to be loaded into the program counter can come from a binary counter, the instruction register, or the output of the ALU.

The x86 is equipped with a variety of addressing modes intended to allow the efficient execution of high-level languages.

There are 50 tens in the number 509.

To handle any possible pattern of calls and returns the number of register windows would have to be unbounded.

True data dependency is also called flow dependency or read after write (RAW) dependency.

Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance.

With a fixed-point notation it is possible to represent a range of positive and negative integers centered on or near 0.

With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range.

With simple, one cycle instructions, there is little or no need for microcode.

With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines.

True

The IAS is the prototype of all subsequent general-purpose computers.

The L1 cache is slower than the L3 cache.

C. execution unit

The Pentium 4 _________ component executes micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers. A. fetch/decode unit B. out-of-order execution logic C. execution unit D. memory subsystem

execution units

The Pentium 4 processor core consists of four major components: fetch/decode unit, out-of-order execution logic, memory subsystem, and __________.

routing

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects. A. link B. protocol C. routing D. physical

error

The QPI link layer performs two key functions: flow control and _________ control.

all of the above

The TL supports which of the following address spaces? A. memory B. I/O C. message D. all of the above

B. memory cycle

The ________ consists of the access time plus any additional time required before a second access can commence. A. latency B. memory cycle time C. direct access D. transfer rate

transfer

The ________ rate is the rate at which data can be transferred into or out of a memory unit.

Harmonic

The _________ Mean is preferred when calculating rates.

control unit

The _________ controls the operation of the CPU and hence the computer.

flow control

The _________ function is needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data.

control

The _________ lines are used to control the access to and the use of the data and address lines.

transaction layer

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer. A. transaction layer B. root layer C. configuration layer D. transport layer

main memory

The _________ stores data. A. system bus B. I/O C. main memory D. control unit

Geometric

The __________ Mean gives consistent results regardless of which system is used as a reference.

Arithmetic

The __________ Mean used for a time-based variable, such as program execution time, has the important property that it is directly proportional to the total time.

System/370

The __________ architecture is the architecture of IBM's mainframe product line.

address lines

The __________ are used to designate the source or destination of the data on the data bus. A. system lines B. data lines C. control lines D. address lines

peripheral component interconnect (PCI)

The __________ is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus.

cache

The __________ is a relatively small fast memory interposed between a larger, slower memory and the logic that accesses the larger memory. A. peripheral B. cache C. processor D. arithmetic and logic unit

speed metric

The __________ measures the ability of a computer to complete a single task. A. clock speed B. speed metric C. execute cycle D. cycle time

I/O

The __________ moves data between the computer and its external environment. A. data transport B. I/O C. register D. CPU interconnection

ALU

The __________ performs the computer's data processing functions. A. Register B. CPU interconnection C. ALU D. system bus

execution

The __________ units execute micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers.

True

The basic function of a computer is to execute programs.

Data storage

The basic functions that a computer can perform are: data processing, data movement, control, and _________.

SPEC CPU2006

The best known of the SPEC benchmark suites is __________ . A. SPEC CPU2006 B. SPECjvm2008 C. SPECsfs2008 D. SPEC SC2013

lines

The cache consists of blocks called __________.

True

The cache holds recently accessed data.

interconnection

The collection of paths connecting the various modules is called the _________ structure.

data bus

The data lines provide a path for moving data among system modules and are collectively called the _________. A. control bus B. address bus C. data bus D. system bus

all of the above

The desktop application(s) that require the great power of today's microprocessor-based systems include___________. A. image processing B. speech recognition C. videoconferencing D. all of the above

Organizational

_________ attributes include hardware details transparent to the programmer. A. Interface B. Organizational C. Memory D. Architectural

CPU

The four main structural components of the computer are: main memory, I/O, system interconnection, and __________.

True

The hierarchical nature of complex systems is essential to both their design and their description.

Architectural

The instruction set, the number of bits used to represent various data types, I/O mechanisms and techniques for addressing memory are all examples of _________ attributes.

all of the above

The interconnection structure must support which transfer? A. memory to processor B. processor to memory C. I/O to or from memory D. all of the above

main memory

The interface between processor and ___________ is the most crucial pathway in the entire computer because it is responsible for carrying a constant flow of program instructions and data between memory chips and the processor. A. main memory B. pipeline C. clock speed D. control unit

B. split cache

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit. A. logical cache B. split cache C. unified cache D. physical cache

ALU

The major structural components of the CPU are: control unit, register, CPU interconnection, and __________.

True

The method of using the same lines for multiple purposes is known as time multiplexing.

hardware failure

The most common classes of interrupts are: program, timer, I/O and ________.

magnetic surface

The most commonly used physical types of memory are: semiconductor memory, __________ memory (used for disk and tape), and optical and magneto-optical.

True

The number of bits used to represent various data types is an example of an architectural attribute.

instruction

The processing required for a single instruction is called a(n) __________ cycle. A. execute B. fetch C. instruction D. packet

True

The raw speed of the microprocessor will not achieve its potential unless it is fed a constant stream of work to do in the form of computer instructions.

geometric

The three common formulas used for calculating a mean are arithmetic, harmonic, and __________

cost

The three key characteristics of memory are capacity, access time, and _______.

memory cycle time

The three performance parameters for memory are: access time, transfer rate, and _________.

False

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.

The unit of transfer must equal a word or an addressable unit

multicore

The use of multiple processors on the same chip is referred to as __________ and provides the potential to increase performance without increasing the clock rate. A. multicore B. GPU C. data channels D. MPC

power management packets

There are three important groups of DLLPs used in managing a link: flow control packets, _________________ , and TLP ACK and NAK packets.

The __________ instruction set is designed to increase the performance of ARM implementations that use a 16-bit or narrower memory data bus and to allow better code density than provided by the ARM instruction set.

Thumb

The most recent, and fastest, peripheral connection technology to become available for general-purpose use is __________, developed by Intel with collaboration from Apple.

Thunderbolt

True

Timing refers to the way in which events are coordinated on the bus.

To achieve greatest performance the memory must be able to keep up with the processor

GPU

Traditionally found on a plug-in graphics card, a _________ is used to encode and render 2D and 3D graphics as well as process video.

1. ________ is used for debugging. A. Direction flag B. Alignment check C. Trap flag D. Identification flag

Trap flag

_________ registers enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.

User-visible

"All instructions should have the 'natural' number of operands" and "all operands should have the same generality in specification" are two criteria that were used in designing the __________ instruction format.

VAX

John von Neumann

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton. A. John Maulchy B. John von Neumann C. Herman Hollerith D. John Eckert

branch prediction

With __________ the processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next.

Geometric

With respect to changes in values, the __________ Mean gives equal weight to all of the values in the data set. A. Harmonic B. Arithmetic C. Composite D. Geometric

With write back updates are made only in the cache.

Associative

_________ is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match, and to do this for all words simultaneously, thus retrieving a word based on a portion of its contents rather than its address.

Structure

_________ is the way in which the components are interrelated.

Base

_________ metric are required for all reported results and have strict guidelines for compilation.

registers

_________ provide storage internal to the CPU. A. Control units B. ALUs C. Main memory D. Registers

Computer Organization

_________ refers to the operational units and their interconnections that realize the architectural specifications.

Little's

__________ Law applies to a queuing system.

High-performance

__________ computing deals with super computers and their software.

Pipelining

__________ enables a processor to work simultaneously on multiple instructions by performing a different phase for each of the multiple instructions at the same time.

speculative execution

__________ enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed.

Amdahl's

__________ law deals with the potential speedup of a program using multiple processors compared to a single processor.

Amdahl's

__________ law deals with the potential speedup of a program using multiple processors compared to a single processor. A. Moore's B. Amdahl's C. Little's D. Murphy's

Virtual

__________ memory is a facility that allows programs to address memory from a logical point of view, without regard to the amount of main memory physically available.

Computer Architecture

__________ refers to those attributes of a system visible to a programmer.

A. Location

__________ refers to whether memory is internal or external to the computer. A. Location B. Access C. Hierarchy D. Tag

Superscalar execution

___________ is the ability to issue more than one instruction in every processor clock cycle.

To ________ a signal is to cause a signal line to make a transition from its logically false (0) state to its logically true (1) state.

assert

Programs written in assembly language are translated into machine language by an _________.

assembler

13. With ____________ any number of instructions may be in the execution stage at any one time up to the maximum degree of machine parallelism across all functional units.

blade server

The I/O function includes a _________ requirement to coordinate the flow of traffic between internal resources and external devices. A. cycle B. status reporting C. control and timing D. data

control and timing

A _________, also known as a branch hazard, occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.

control hazard

14. The _____________ must control the state of the instruction cycle.

control unit

2. The ____________ of a processor causes the processor to step through a series of micro-operations in the proper sequence, based on the program being executed.

control unit

3. The _________ of a processor generates the control signals that cause each micro-operation to be executed.

control unit

The ________ controls the movement of data and instructions into and out of the processor. A. control unit B. ALU C. shifter D. branch

control unit

The major components of the processor are an arithmetic and logic unit (ALU) and a __________.

control unit (CU)

The _________ element is needed to transfer data between the various registers and the ALU.

internal processor bus

An instruction cycle includes the following stages: fetch, execute, and _______.

interrupt

5. The six things needed to specify the function of a processor are: operations (opcodes), addressing modes, registers, I/O module interface, memory module interface, and ________.

interrupts

Individual variables, compiler assigned global variables, register addressing, and multiple operands addressed and accessed in one cycle are characteristics of __________ organizations.

large register file

The rightmost digit is called the _________ digit.

least significant

1. A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence. A. loop buffer B. delayed branch C. multiple stream D. branch prediction

loop buffer

A ________ is defined to be the time it takes to fetch two operands from registers, perform an ALU operation, and store the result in a register.

machine cycle

The operation of the processor is determined by the instructions it executes, referred to as _________ or computer instructions.

machine instructions

We can broadly classify external devices into three categories: human readable, communication, and __________.

machine readable

1. The prefix __________ refers to the fact that each step is very simple and accomplishes very little.

micro

6. Each of the smaller cycles involves a series of steps, each of which involves the processor registers, referred to as _________.

micro-operations

In the operation of the Intel Core each instruction is translated into one or more fixed-length RISC instructions known as _________.

micro-operations (or micro-ops)

In any number, the leftmost digit is referred to as the __________ digit because it carries the highest value.

most significant

Instruction-level parallelism is also determined by __________, which is the time until the result of an instruction is available for use as an operand in a subsequent instruction.

operation latency

The _________ connects multiple inputs to a single output.

multiplexer

9. The ________ protects critical data used by the operating system from user applications separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only, and detecting unexpected memory accesses that could potentially break the system.

multithreading

Although a variety of different approaches to reduced instruction set architecture have been taken, certain characteristics are common to all of them: register-to-register operations, simple addressing modes, simple instruction formats, and __________.

one instruction per cycle

13. From the point of view of an A15 core, an interrupt can be active, inactive, or __________ .

pending

A self-contained computer program that is incorporated into a larger program is a __________.

procedure

The categories for the major functions or requirements for an I/O module are: control and timing, device communication, data buffering, error detection, and _________.

processor communication

Source and result operands can be in one of four areas: main or virtual memory, immediate, I/O device, and _________.

processor register

The work that has been done on assessing merits of the RISC approach can be grouped into two categories: quantitative and _________.

qualitative

Another term for "base" is __________. A. radix B. integer C. position D. digit

radix

Given ( . . . a3a2a1a0.a-1a-2a-3 . . . )r, the dot between a0 and a-1 is called the ________.

radix point

Extending the range of numbers that can be expressed by increasing the bit length is referred to as __________.

range extension

There are four types of I/O commands that an I/O module may receive when it is addressed by a processor: control, test, write, and _________.

read

10. The _________ predicts the instruction stream fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.

resource ownership

The ________ flag allows the programmer to disable debug exceptions so that the instruction can be restarted after a debug exception without immediately causing another debug exception.

resume

Committing or _________ the instruction is when instructions are conceptually put back into sequential order and their results are recorded.

retiring

An asynchronous counter is also referred to as a ________ because the change that occurs to increment the counter starts at one end and "ripples" through to the other end.

ripple counter

__________ is when the result is put back into the floating-point format and the extra bits must be eliminated in such a way as to produce a result that is close to the exact result.

rounding

A ________ controls multiple high-speed devices and, at any one time, is dedicated to the transfer of data with one of those devices.

selector channel

The difference between the operations provided in high-level languages (HLLs) and those provided in computer architecture is known as the ________.

semantic gap

In a ________ interface there is only one line used to transmit data and bits must be transmitted one at a time.

serial

"To subtract one number from another, take the twos complement of the subtrahend and add it to the minuend" is the _________ rule.

subtraction

A ________ is used to connect storage systems, routers, and other peripheral devices to an InfiniBand switch. A. target channel adapter B. InfiniBand switch C. host channel adapter D. subnet

target channel adapter

Lihat semua set pelajaran

CS 330

Set pelajaran terkait

SUR270 Pharmacology CST Prep

Domain 4- Virtualization and Cloud Computing

Leadership Mgmt HESI EAQ

Art 202 Test 2

Real Estate Chapter 1&2

WPC 480 Midterm

Section 12 Quiz Database Programming With SQL

Natural Selection

EMT - Prehospital Emergency Care: Part 2: Anatomy, Physiology, and Medical Terminology: Chapter 7: Anatomy, Physiology, and Medical Terminology

Ch. 7 - Study Guide

ACCT 201 Final Exam

Marketing Ch. 1 Learn Smart

Blockchain & Bitcoin

final study guide

Football (soccer) Vocabulary Nouns

A&P Ch 9: The Nervous System: The Brain & Cranial Nerves

ISTQB - Automation - 1.1 Purpose of Test Automation

Database management test 1

Chapter 5

Immunity HESI Exit Practice