Digital Circuits Exam 2

Combinational Circuit Design

-Determine required number of inputs and outputs from the specifications. -Derive the truth table for each of the outputs based on their relationships to the input. -Simplify the boolean expression for each output. Use Karnaugh Maps or Boolean algebra. -Draw a logic diagram that represents the simplified Boolean expression. Verify the design by analysing or simulating the circuit.

Multi-Level Circuits

1. AND-OR circuit means a two-level circuit composed of a level of AND gates followed by an OR gate at the output. 2. OR-AND circuit means a two-level circuit composed of a level of OR gates followed by an AND gate at the output. 3. OR-AND-OR circuit means a three-level circuit composed of a level of OR gates followed by a level of AND gates followed by an OR gate at the output. 4. Circuit of AND and OR gates implies no

Minterms

A Boolean expression resulting in 1 for the output of a single cell, and 0s for all other cells in a Karnaugh map, or truth table.

Maxterms

A Boolean expression resulting in a 0 for the output of a single cell expression, and 1s for all other cells in the Karnaugh map, or truth table.

Multiplexer (MUX) (Data Selector)

A combinational logic circuit designed to switch one of several input lines through to a single common output line by the application of a control signal

Two Level Multiple Output Circuits

A function written in sum-of-products form or in product-of-sums form

Configurable Logic Block

A fundamental building block of field-programmable gate array. Requires I/O

Bus Notation

A network topology or circuit arrangement in which all devices are attached to a line directly and all signals pass through each of the devices.

Sum-of-Products (SOP)

A type of Boolean expression where several product terms are summed (OR'ed) together.

Product-of-Sums (POS)

A type of Boolean expression where several sum terms are multiplied (AND'ed) together.

Complete Gate Set

A well-known complete set of connectives is { AND, NOT }, consisting of binary conjunction and negation

Lookup Table (LUT)

An array of data that maps input values to output values, thereby approximating a mathematical function. Given a set of input values, a lookup operation retrieves the corresponding output values from the table

HI Z (High Impedence)

An output signal state in which the signal is not being driven. The signal is left open, so that another output pin (e.g. elsewhere on a bus) can drive the signal or the signal level can be determined by a passive device

Prime Implicant

By finding all permitted (integer power of 2) maximum sized groups of min-terms.

Essential Prime Implicant

By identifying those prime implicants that contain at least one min-term not found in any other prime implicant.

Tri State Buffers (3 State Buffers)

Can be thought of as an input controlled switch with an output that can be electronically turned "ON" or "OFF" by means of an external "Control" or "Enable" ( EN ) signal input

Macrocell

Contains logic implementing disjunctive normal form expressions and more specialized logic operations.

OR-AND

F = (A + B + C)(A + B′ + C′)(A + C′ + D)

AND-NOR

F = (A′B′C′ + A′BC + A′CD′)′

NAND-AND

F = (A′B′C′)′ ∙ (A′BC)′ ∙ (A′CD′)′

NOR-OR

F = A + (B′ + C)′ + (B + C′ + D′)′

AND-OR

F = A + BC′ + B′CD

NOR-NOR

F = [(A + B + C)′ + (A + B′ + C′)′ + (A + C′ + D)′]'

NAND-NAND

F = [A′ ∙ (BC′)′ ∙ (B′CD)′]′

OR-NAND

F = [A′ ∙ (B′ + C) ∙ (B + C′ + D′)]′

PLA Program Table

Has a programmable AND gate array and programmable OR gate array.

PAL Structure

Has a programmable AND gate array but fixed OR gate array.

Read Only Memory (ROM)

Has fixed AND gate array but programmable OR gate array. Consists of an array of semiconductor devices that are interconnected to store an array of binary data

Decoders

Is a circuit that changes a code into a set of signals. It does the reverse of encoding

Function Block

Is a graphical language for programmable logic controller design, that can describe the function between input variables and output variables.

CPLD Structure and Use

Is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The main building is a macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. Used for loading the configuration data of a field programmable gate array from non-volatile memory.

Field Programmable Gate Arrays (FPGA) Structure and Use

Is an electronic component used to build reconfigurable digital circuits. That means that it is different from a logic gate, because a logic gate has a fixed function.

Gate Delay

Is the length of time which starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change

Dynamic Hazards

Is the possibility of an output changing more than once as a result of a single input change.

Programmable Logic Array Structure

Is used for implementation of various combinational circuits using buffer, AND gate and OR gate.

NAND Gate

Logic circuit that operates like an AND gate followed by an INVERTER. The output of a NAND gate is LOW (logic level 0) only if all inputs are HIGH (logic level 1).

NOR Gate

Logic circuit that operates like an OR gate followed by an INVERTER. The output of a NOR gate is LOW (logic level 0) when any or all inputs are HIGH (logic level 1).

Active Low

Means that signal will be performing its function when its logic level is 0

Active High

Means that signal will be performing its function when its logic level is 1

Multiplexer Combinational Circuit Implementation

Performs the function of selecting the input on any one of 'n' input lines and feeding this input to one output line.

Priority Encoders

Take all of their data inputs one at a time and converts them into an equivalent binary code at its output.

Two Level Forms

That any path from input to output contains maximum two gates

Decoder Combinational Circuit Implementation

That has 'n' input lines and maximum of 2n output lines. One of these outputs will be active High based on the combination of inputs present, when Enabled.

Alternative Gate Symbols

The inversion "bubble" is at the input or the output

Limited Gate Fan in

The number of inputs a logic gate can handle

Static Zero Hazards

The output is currently 0 and after the inputs change, the output momentarily changes to 1,0 before settling on 0

Static One Hazards

The output is currently 1 and after the inputs change, the output momentarily changes to 0,1 before settling on 1

Multi-Level NAND and Multi-Level NOR

Two-level circuits consisting of AND and OR gates can easily be converted to networks that can be realized only NAND and NOR gates

Timing Diagrams

Used to show interactions when a primary purpose of the diagram is to reason about time; it focuses on conditions changing within and among lifelines along a linear time axis