Digital Logic Circuits Final
A+(BCD') =
(A+B)(A+C)(A+D')
What is the decimal value of the 4-bit, 2's complement code 0010?
+2
For the number 261.367, what position (p) is the number 3 in?
-1
What is the decimal value of the 8-bit, 2's complement code 1111 1110?
-2
For the number 261.367, what position (p) is the number 7 in?
-3
For the number 261.367, what position (p) is the number 1 in?
0
For the following resistor driver configuration, how much output current (Io) will flow when the gate drives a logic HIGH.
0 amps
What is the radix of the decimal number system?
10
If the number 261.367 has a radix of 10, what is the weight of the position containing the numeral 2?
100
What is the 8-bit, 2's complement code for -110?
1111 1111
What is the radix of the hexadecimal number system?
16
For the number 261.367, what position (p) is the number 2 in?
2
If the number 101.111 has a radix of 2, what is the weight of the position containing the bit 0?
2
What is the radix of the binary number system?
2
How many select lines are needed in a 1-to-64 demultiplexer?
6
What is the radix of the octal number system?
8
A+ABC'+AD =
A
AB+AB' =
A
Mealy Machine
A finite state machine (FSM)that determines its outputs from the present state and from the inputs.
What allows a finite state machine to make more intelligent decisions about the system outputs compared to combinational logic alone?
A finite state machine has knowledge about the past inputs.
Take a look around right now and identify two digital technologies in use.
A smart phone, tablet or computer and Data transmitted over WiFi or hard-wired internet
Moore Machine
A state machine whose output is determined only by the sequential logic of the machine.
(A+BC')' =
A'(B'+C)
(A+B')+CD =
A+(B'+CD)
AB+A'C+BC =
AB+A'C
Why is abstraction an essential part of engineering design?
Abstraction allows the details of the implementation to be hidden while the higher-level systems are designed. Without abstraction, the details of the implementation would overwhelm the designer
What is the only source of delay mismatch from the inputs to the outputs in a programmable array?
An input may or may not go through an inverter before reaching the AND gates
If an electrical signal is a direct function of a physical quantity, is it considered analog or digital?
Analog
Is the electrical signal that travels down earphone wires analog or digital?
Analog
Is the sound coming out of earbuds analog or digital?
Analog
Is the voltage coming out of the battery in an iPod analog or digital?
Analog
What part of any system will always require an analog component?
Any electrical components that must interact or interface with the physical world
What is the name of the number system containing 10 base 2?
Binary
What is the difference between types Boolean {TRUE, FALSE} and bit {0, 1}?
Boolean is used for decision making constructs (when, else) while bit is used to model real digital signals.
In a decoder, a logic expression is created for each output. Once all of the output logic expressions are found, how can the decoder logic be further minimized?
By identifying any logic terms that are used in multiple locations (inversions, product terms, and sum terms) and sharing the interim results among multiple circuits in the decoder
Name the type of programmable logic described by the characteristic: this device combines multiple PALs on a single chip with a partitioned interconnect system.
Complex Programmable Logic Device (CPLD)
Why is concurrency such an important concept in HDLs?
Concurrency is necessary to model real systems that operate in parallel.
What is the name of the number system containing 10 base 10?
Decimal
Which of the following four number systems could the number 88 be part of? Give all that are possible.
Decimal Hexadecimal
Which of the following four number systems could the number 99 be part of? Give all that are possible.
Decimal Hexadecimal
If an electrical signal is a discrete representation of information, is it considered analog or digital?
Digital
Is the MP3 file stored on an iPod analog or digital?
Digital
Is the circuitry that reads the MP3 file from memory on an iPod analog or digital?
Digital
Name the type of programmable logic described by the characteristic: this device adds an output logic macrocell to a traditional PAL.
Generic Array Logic (GAL)
Why did digital designs move from schematic-entry to text-based HDLs?
HDL models could be much larger by describing functionality in text similar to traditional programming language.
Name the type of programmable logic described by the characteristic: this device is a PAL or GAL that is programmed during manufacturing.
Hard Array Logic (HAL)
What is the name of the number system containing 10 base 16?
Hexadecimal
All logic functions can be implemented equivalently using either a canonical sum of products (SOP) or canonical product of sums (POS) topology. Which of these statements is true with respect to selecting a topology that requires the least amount of gates?
If a minterm list has over half of its row numbers listed, a POS topology will require fewer gates than SOP.
Why does the output logic stage of a finite state machine always use the current state as one of its inputs?
If it didn't, it would simply be a separate combinational logic circuit and not be part of the finite state machine.
Which of the following describes the situation in which a static-0 timing hazard may occur?
In a Product of Sums topology implemented with a minimal product.
Which of the following describes the situation in which a static-1 timing hazard may occur?
In a Sum of Products topology implemented with a minimal sum.
What impact does adding an additional state have on the implementation of the state memory logic in a finite state machine?
It adds a new state code that must be supported
Why don't we need to explicitly include the STANDARD package when creating a VHDL design?
It defines the base functionality of VHDL so its use is implied.
How can the output of a DUT be verified when it is connected to a signal that does not go anywhere?
It is viewed in the logic simulator as either a waveform or text listing.
Why does modeling combinational logic in its canonical form with concurrent signal assignments with logical operators defeat the purpose of the modern digital design flow?
It requires the designer to first create the circuit using the classical digital design approach and then enter it into the HDL in a form that is essentially a text-based netlist. This doesn't take advantage of the abstraction capabilities and automated synthesis in the modern flow.
Which of the following statements about the next state logic is FALSE?
It uses the results of the output logic as part of its inputs.
What impact does asserting a reset have on a finite state machine?
It will set the current state code to all zeros.
Logic minimization is accomplished by removing variables from the original canonical logic expression that don't impact the result. How does a Karnaugh map graphically show what variables can be removed?
K-maps rearrange a truth table so that adjacent cells have one and only one input variable changing at a time. If adjacent cells have the same output value when an input variable is both a 0 and a 1, that variable has no impact on the interim result and can be eliminated.
Name a technology or device that has evolved from analog to digital in your lifetime.
Music Storage (records to MP3/MP4)
If it is desired to have the outputs of an encoder produce 0's for all input codes not defined in the truth table, can "don't cares" be used when deriving the minimized logic expressions? Why?
No. Each cell in the K-map corresponding to an undefined input code needs to contain a 0 so don't cares are not applicable.
Does the delay of a combinational logic circuit change based on the input values that the circuit is evaluating?
No. Even though for some input code transitions the circuit may be able to compute the final output faster because the corresponding signal paths being used have shorter delay, the overall delay of the circuit is always defined as the longest delay path.
Does the delay specification of a combinational logic circuit change based on the input values that the circuit is evaluating?
No. The delay is always specified as the longest delay path.
Give three advantages of using digital systems over analog.
Noise Immunity, Simple Circuit Design Low Power
What is the name of the number system containing 10 base 8?
Octal
Which of the following four number systems could the number 22 be part of? Give all that are possible.
Octal Decimal Hexadecimal
Name the type of programmable logic described by the characteristic: this device has a programmable AND-plane and fixed OR-plane.
Programmable Array Logic (PAL)
Name the type of programmable logic described by the characteristic: this device has a programmable AND-plane and programmable OR-plane.
Programmable Logic Array (PLA)
Which D-Flip-Flop timing specification is most responsible for the ripple delay in a ripple counter?
TCQ
What does the term metastability refer to in a sequential storage device?
That the device can exist in an unstable state when undisturbed.
What is the primary difference between an FPGA and a CPLD?
The abundance of configurable routing
A fan-out specification is typically around 6-12. If a logic family has a maximum output current specification of IO-max¼25mA and a maximum input current specification of only II-max¼1uA, a driver could conceivably source up to 25,000 gates (IO-max/II-max ¼ 25mA/ 1uA ¼ 25,000) without violating its maximum output current specification. Why isn't the fan-out specification then closer to 25,000?
The fan-out specification is in place for AC behavior. It ensures that the AC loading on the driver doesn't slow down its output rise and fall times. If too many loads are connected, the output transition will be too slow, and it will reside in the uncertainty region for too long leading to unwanted switching on the receivers.
In the 3-state buffer circuit shown, assuming DATA=1 and EN=0, what is the state of the output, and why?
The output is in the Z state because both the PMOS and NMOS transistors are turned off whenever EN=0.
A "Don't Care" can be used to minimize a logic expression by assigning the output of a row to either a 1 or a 0 in order to form larger groupings within a K-map. How does the output of the circuit behave when it processes the input code for a row containing a don't care?
The output will be whatever value was needed to form the largest grouping in the K-map.
How are the product terms in a multiplexer based on the identity theorem?
The select line inputs will produce 1's on the inputs of the selected product term. This allows the input signal to pass through the selected AND gate because anything AND'd with a 1 is itself.
What is the risk of running the clock above its maximum allowable frequency in a finite state machine?
The setup and hold specifications of the D-Flip-Flops may be violated, which may put the machine into an unwanted state.
What is the downside of using D-Flip-Flops that do not have preset capability in a finite state machine?
The start-up state can never have a 1 in its state code.
When designing a finite state machine, many of the details of the implementation can be abstracted. At what design step do the details of the implementation start being considered?
The state memory synthesis step.
What characteristic of a counter makes it a special case of a finite state machine?
The state transitions are mostly linear, which reduces the implementation complexity
How long do you need to wait for all hazards to settle out?
The time equal to the longest delay path in the circuit.
Why does VHDL support modeling techniques that aren't synthesizable?
VHDL needs to support all steps in the modern digital design flow, some of which are unsynthesizable such as test pattern generation and timing verification.
If a digital signal is only a discrete representation of the real information, how is it possible to produce high quality music without hearing "gaps" in the output due to the digitization process?
When the digital music is converted back to analog sound the gaps are smoothed out since an analog signal is by definition continuous.
When does the magnitude of electrical noise on a digital signal prevent the original information from being determined?
When the magnitude of the noise is large enough that it causes the signal to inadvertently cross the threshold voltage.
Does the use of components model concurrent functionality? Why?
Yes. The components are treated like independent sub-systems whose behavior runs in parallel just as if separate parts were placed in a design.
An encoder is
a system that has a greater number of inputs than outputs. A compressed output code is produced based on which input(s) lines are asserted.
A decoder is
a system that has a greater number of outputs than inputs. The behavior of each output is based on each unique input code.
multiplexer
a system that has one output and multiple inputs. At any given time, one and only one input is routed to the output based on the value on a set of select lines. For n select lines, a multiplexer can support 2 n inputs.
demultiplexer
is a system that has one input and multiple outputs. The input is routed to one of the outputs depending on the value on a set of select lines. For n select lines, a demultiplexer can support 2n outputs.
Using the data sheet excerpt below, give the maximum propagation delay from low to high (tPLH) for the 74HC04 inverter when powered with VCC=+2v.?
tpd = 95 ns
Which D-flop-flop timing specification requires all of combinational logic circuits in the system to settle on their final output before a triggering clock edge can occur?
tsetup
