Digital_2
CMOS
- Complimentary Metal Oxide Semi- conductor - require less power than TTL - Wide "HIGH" operating range (+3V to +18V)
Shift registers can form useful counters by recirculating a pattern of 0's and 1's. Two important shift register counters are the ___________ and the _____________.
- Johnson counter - Ring counter
R-S FLIP-FLOP
- RS latches - level activated, and have just two inputs
RAM
- Random access memory - temporary data storage. - read/ write memory and can store data only when power is applied. - Volatile. have two categories ( SRAM, DRAM)
UART
- Universal Asynchronous Receiver Transmitter. A device that turns serial data into parallel data. The cornerstone of serial ports and modems.
Latch circuit
- asynchronous -level trigger. the output of the present state and input of the next state depends on the level that is binary input 1 or 0
Ring Counter
- can also be implemented with either D flip-flops or J-K flip-flops
Johnson counter
- can be made with a series of D flip-flops - can be made with a series of twist J-K flip flops - unique states (modulus) = 2n(number of flip flops) - it is useful when need a sequence that changes by only one bit at a time but it has a limited number of states (2n)
Trouble shooting digital systems
- fault detection - fault isolation - fault correction
The 555 timer
- including as a one shot, the pulse width ( tw = 1.1 x R1 x C1) (has just one resistor) - astable multivibrator( pulse oscillator) , [f= 1.44/ ((R1+2R2)C1)]
A reconstruction filter ______________.
- is a low- pass filter - can have the same response as an anti-aliasing filter - smoothes the output from a DAC
The Q0 output of the counter shown ________________.
- is present before Q1 or Q2 - changes on every clock pulse - has a higher frequency than Q1 or Q2
One-Shots
- monostable multivibrator is a device with only one stable state. - When triggered, it goes to its unstable state for a predetermined length of time, then returns to its stable state. - For most one-shots, the length of time in the unstable state( tw) is determined by an external RC circuit. - Non retriggerable ( donot respond to any triggers that occur during the unstable state) - Retriggerable (respond to any trigger, even if it occurs in the unstable state) -An application for a retriggerable one shot is a power failure detection circuit
Test equipment
- oscilloscope - logic pulser - logic probe - current tracer
Advantage of PLD
- reduced complexity of circuit board. - lower power requirements - less board space - simpler testing procedures - higher reliability - design flexibility
Advantage of ring counter
- self decoding with a unique output for each state at the Q of each flip flop
External IC faults- shorted signal lines
- sloppy wiring - solder bridges - incomplete etching
A 4-bit parallel-in / parallel-out shift register will store data for ________ clock period.
1 clock period
The number of comparators required in a 10 bit flash ADC is _______.
1023
A 4- bit binary counter has a terminal count of ___________.
15
Assume the input frequency (fin) is 256HZ. The output frequency (fout) will be ____________.
1HZ
FF2 represents the MSB. The counts that are being decoded by the 3-input AND gates are ________________.
3 and 6
Assume the clock for a 4-bit binary counter is 80 KHZ. The output frequency of the fourth state (Q3) is ________.
5KHZ
Master-Slave Flip Flop
A master-slave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. the second latch in the series only changes in response to a change in the first (master) latch
A sigma-delta circuit is a form of ___________.
ADC ( Analog to Digital convertor)
Analog and digital conversion
Block x is a digital to analog converter block y is an analog to digital converter
The circuit shown is a __________.
DAC
Assume Q0 is LOW. The next clock pulse will cause ____________.
FF1 and FF2 to both latch
The circuit shown is a __________.
Johnson counter
For the circuit shown, the input on the far left is for the ____________.
LSB (least significant bits)
FMS
Loading Flight Management System - A disk data loader - A PMAT program loaded on a laptop - transfer the database from one FMS computer to the other ( no external connections). This is usually done if one FMS is found to have corrupt or missing data and the database in the other unit has the current database
To cause a D flip-flop to toggle, connect the ___________.
Not Q output to the D input
PROMs
PROMs are programmable ROM, in which a fused link is burned open during the programming process. Once the PROM is programmed, it cannot be reversed.
The 7493 A asynchronous counter diagram is shown (J and K are HIGH). To make the count have a modulus of 16, connect _______________.
Q0 to CLK B
ROM
Read Only Memory The ROM family is all considered non-volatile, because it retains data with power removed. - mask rom - programmable rom (PROM) - erasable prom (EPROM) - ultraviolet eprom (UV EPROM) - electrically erasable prom (EEPROM) ROM is checked using the checksum method - to read a value from the ROM, an address is placed on the address bus, the chip is enabled, and a short time later (called the access time), data appears on the data bus
Asynchronous Static RAM
Read cycle sequence: - a valid address is put on the address bus - chip select is LOW - output enable is LOW - data is placed on the data bus Write cycle sequence: - a valid address is put on the address bus - chip select is LOW - write enable is LOW - data is placed on the data bus
Flash ADC
The flash ADC uses a series high-speed comparators that compare the input with reference voltages. Flash ADCs are fast but require (2^n) - 1 comparators to convert an analog input to an n-bit binary number. for example, how many comparators are needed by a 10-bit flash ADC? 1023
Fan in
The number of inputs of a gate that it can handle without impairing its normal operation
Modulus
The number of unique states through which a counter will sequence.
4 Bit bidirectional shift register
The shift direction is determined by which gates are enabled. A HIGH on the Right/left caused G1-G4 to be ready.... allows the input to go to the next gate (shift right). A LOW on this causes G5- G8 to be ready sending an input to the preceding gate (shift left). The data word can be seen changing on the parallel output at every clock pulse.
Zero suppression
Zero suppression is the removal of redundant zeroes from a number. This can be done for storage, page or display space constraints or formatting reasons, such as making a letter more legible
The block diagram is for a successive- approximation ADC. The top block is ________.
a DAC
The 74138 decoder can also be used as ___________.
a DEMUX
Anti-aliasing filter
a low-pass filter that limits high frequencies in the input signal to only those that meet the requirements of the sampling theorem.
Stack
a portion of RAM is devoted to this type of memory it is very useful for temporary storage of internal registers, so that the processor can be interrupted but can easily return to a given task.
Output Enable (bar OE)
active during a read operation, otherwise it is inactive. it connects the memory to the data bus.
In order to read or write to a specific memory location, a binary code is placed on the ______________.
address bus, which is a group of conductors with a common function.
The location of a unit of data in a memory is called the __________.
address. - a byte is the smallest unit of data that can be accessed. for example the blue byte is located in row 7.
Reconstruction filter
after converting a digital signal to analog, it is passed through a low-pass " reconstruction filter" to smooth the stair steps in the output.
The circuit illustrated is a ______.
astable multivibrator
The counter shown below is an example of ___________.
asynchronous counter
Magnetic hard drive
backbone of computer mass storage and is applied to other devices such as digital video recorders. platters are arranged in tracks (circular shapes) , sectors (pie shaped) Files are listed in a FAT ( file allocation table) that keeps track of file names, locations , size and more.
The ADC804 integrated circuit signals a completed conversion by __________.
bar INTR goes LOW
Examples of memory address in a 2-dimensional memory array.
blue bit indicates memory cell
Collection of resistors, diodes, and transistors fabricated on a single piece of semi conductor material (usually silicon) called a substrate which is commonly referred to as a _____.
chip
Demultiplexer
combinational logic circuit that receives binary information on a single input and sends this information to one of many possible output lines. The output is selected by the binary value on the select lines
Multiplexer
combinational logic circuit that selects binary information from one of many input lines and directs it to a single output line.
Optical storage
compact disk (CD) uses a laser to burn tiny pits into the media. surrounding the pits are flat areas called lands. binary data is encoded with a special method called negative non-return to zero encoding.
If you expand two 4-bit comparators to accept two 8-bit numbers, the output of the least significant comparator is ________________________________________.
connected to the cascading inputs of the most significant comparator
A re-triggerable one-shot with an active HIGH output has a pulse width of 20ms and is triggered from a 60HZ line. The output will be a __________.
constant HIGH
The read operation is actually a ______ operation.
copy. the original data is not changed. The data bus is a "two-way" path; data moved from the memory during a read operation.
The 74HC 164 has two serial inputs. If data is placed on the A input, the B input ____________
could serve as an active HIGH enable
CTR DiV 16 indicates a ______________.
counter with sixteen states
Internal decoders decode the address to determine the specific location. Data is then moved to or from the _____________.
data bus
The application illustrated is a _______.
data storage device
Resolution
defined as the reciprocal of the number of steps in the output for example, what is the resolution of the BCN31 R-2R ladder network, which has 8-bits? 2^8 - 1 = 255 1/255 = 0.39%
DSP
digital signal processor is optimized for speed and working in real time
DIMM
dual in line memory modules have a 64-bit data path with I/O on both sides of the board
DRAM
dynamic random access memory - bits stored as charge on a capacitor - simple and cost effective, but require refresh circuitry to prevent losing data. - The address lines are multiplexed to reduce the number of address lines. - a feature with some DRAM is fast page mode. Fast page mode allows successive read write operations from a series of columns address that are all on the same row main memory
The output of a D latch will not change if __________.
enable is not active
EPROMs
erasable PROM and can be erased by exposure to UV light through a window. To program it, a high voltage is applied to Vpp and bar OE is brought LOW.
An EPROM has a window to allow UV light to enter under certain conditions. The purpose of this is to _____________.
erase the data
An anti-aliasing filter should have ______________.
fc less than 1/2 fsample
FAT
file allocation table
On a hard drive. information about file names, locations, and file size are kept in a special location called the ________________.
file allocation table (FAT)
FIFO
first in first out memory arrangement of shift register, used in applications where two systems communicate at different rates.
Flash memory
high density read/ write memories that are nonvolatile. have the ability to retain charge for years with no applied power. uses a MOS transistor with a floating gate as the basic storage cell one drawback to flash memory is that once a bit has been set to 0, it can be reset to a 1 only by erasing an entire block of memory
In order to recover a signal, the sampling rate must be greater than twice the highest frequency in the signal.
if the signal is sampled less than this, the recovery process will produce frequencies that are entirely different than in the original signal. These "masquerading" signals are called aliases.
A DSP is a specialized microprocessor that ___________.
is designed to be very fast
Universal shift register
it has both serial and parallel input and output capability. The 74HC194 is an example of a 4 bit bidirectional universal shift register.
The advantage of dynamic RAM over static RAM is that _________.
it is simpler and cheaper
Disadvantage of ring counter
it must be preloaded with the desired pattern ( usually a single 0 or 1) and it has even fewer states than a Johnson counter (n).
Stack pointer
keeps track of the location that data was last stored on the stack. This will be the next data to be taken from the stack when needed
LIFO
last in first out memory
If an anti-aliasing filter is not used in digitizing a signal the recovery process?
may include alias signals
Memory unit
memories store data in units from one to eight bits. the most common unit is the byte, which by definition is 8 bits.
Sampling
most input signals to an electronic system start out as analog signals. For processing, the signal is normally converted to a digital signal by sampling the input. Before sampling, the analog input must be filtered with a low-pass anti-aliasing filter.
Write operation
new data overwrites the original data. Data moves to the memory.
Propagation delay increases with ______________.
number of inputs.
Synchronous
occurring at the same time
Stage
one storage element in a register
The output enable signal (NOT OE) on a RAM is active _____________.
only during a read operation
The first step in a read or write operation for a random access memory is to _________________.
place a valid address on the address bus
PLD
programmable logic devices - SPLD (simple PLD), are the earliest type of array logic used for fixed functions and smaller circuits with a limited number of gates. - CPLD (complex PLD), are multiple SPLD s arrays and interconnection arrays on a single chip. - FPLD (field programmable gate array), are a more flexible arrangement than CPLDs with much larger capacity.
The two main memory operations are called _____ and ______.
read and write.
A nonvolatile memory is one that __________.
retains data without power applied
Read Enable (bar RE) and Write Enable ( bar WE)
signals are sent from the CPU to memory to control data transfer to or from memory
SIMM
single in line memory modules have a 32-bit data path with I/O on only one side
SRAM
static random access memory - bits stored in a semiconductor latch or flip-flop - more faster than DRAM but is more complex , takes up more space and more expensive. L2 cache
The time interval illustrated is called _______.
t(PLH)
Analog to digital conversion
the analog signal is converted to digital form after the anti-aliasing filter - first step: converting a signal to digital form is to use a sample and hold circuit. - second step: quantize these staircase levels to binary coded form using an analog to digital converter (ADC)
Terminal count ( if 4 bit)
the final state in a counter's sequence ( answer is 15)
Nyquist
the highest signal frequency that can be sampled
Fan out
the maximum number of digital inputs that the output of a single logic gate can feed & the gate must be from same logic family
Quantization
the process whereby a binary code is assigned to each sampled value during analog to digital conversion
Using two ICs as shown will expand ________.
the word size
Tri- State devices
this kind of device include a third electrical state called high impedance or Hi- Z - tri state provides a way to have two or more logic gate outputs connected together.
Parallel load shift register ( serial/ parallel to serial)
this unit can also be used as a serial to serial register. shift=1 / load= 0
Load
to enter data in a shift register
Shift
to move binary data from stage to stage within a shift register or other storage device or to move binary data into or out of the device
The D flip flop shown will
toggle on the next clock pulse
The small triangles on the logic diagram indicate that these outputs are __________
tri-stated
When data is read from RAM, the memory location is ___________-.
unchanged
Chip Select (bar CS) or Chip Enable (bar CE)
used as part of address decoding. all other inputs are ignored of the chip select is not active.
Static RAM is ________.
volatile read/ write memory
The decimal-to-binary encoder shown does not have a zero input. This is because __________.
when zero is the input, all lines should be LOW
EEPROMs
which can be erased and programmed with electrical pulses
Computer memories are organized into multiples of bytes called __________.
words. a word is equal to the internal register size ( usually 16, 32 or 64 bits) 32bit called double word 64bit called quad word
External IC faults- open signal lines
- broken wire - poor solder connection - crack or cut trace on a printed circuit board - bent or broken pin on an IC
Flip flops circuit
- synchronous - edge trigger flip flops require a trigger pulse or clock pulse in order to change their output state.
T Flip-flop
- toggle flip-flop - When input T= 0 the output Q retain its previous value. - When input T=1 the output Q inverts on every tick of the clock - When inputs J and K of a K-K flip-flop are connected together, the J-K flip-flop will behave like a T flip-flop.
TTL
- transistor- transistor logic. - uses positive logic (1= +5V)
A possible sequence for a 4-bit Johnson counter is _______________.
.... 1000, 1100, 1110 ......
Assume the output is initially HIGH on a leading edge triggered J-K flip flop. For the inputs shown, the output will go from HIGH to LOW on which clock pulse?
3
Flip-flops
A flip flop differs from a latch in the manner is changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered.
Basic shift register operations
A shift register is an arrangement of flip-flops with important applications in storage and movement of data.
The output will be LOW if ________.
A<B , A>B
Assume you want to decode the binary number 0011 with an active-HIGH decoder. The missing gate should be _______.
AND gate
How could you test two 4-bit numbers for equality?
AND the outputs of four XNOR gates
Encoder
An encoder accepts an active logic level on one of its inputs and converts it to a coded output, such as BCD or binary
BITE
Built In Test Equipment - form of self diagnostic - simple as go/ no go ( green or red led on an LRU) - tree types power up BITE Background BITE Tech initiated BITE
The most common type of package is the ____________ which consists of two parallel rows of pins.
Dual Inline Package (DIP)
Serial in/ serial out shift register
Each clock pulse will move an input bit to the next flip-flop.
What is happen when the short between two pins?
IC will force the logic signals at those pins always to be identical
Hysteresis
Level sensitive with output switching state at two distinct trigger levels, called lower trigger level (VT-) and upper trigger level (VT+). - The difference between the two trigger levels is hysteresis (VT+ - VT-)
Assume you want to decode the binary number 0011 with an active-LOW decoder. The missing gate should be _______.
NAND gate
The circuit shown is a ____________.
Parallel-in/ serial- out shift register
A simple rule for the D latch is ___________.
Q follows D when the Enable is active
Categories of ICs
SSI - Small Scale Integration (Fewer than 12 gates) MSI - Medium Scale Integration (12 to 99 gates) LSI - Large Scale Integration (100 to 9999 gates) VLSI - Very Large Scale Integration (10000 to 99999 gates) ULSI - Ultra large scale integration (100000 or more gates)
For the full-adder shown, assume the input bits are as shown with A=0, B=0, C in =1. The Sum and C out will be _________.
Sum=1 C out = 0
Flip flops
Synchronous inputs are transferred in the triggering edge of the clock ( for example the D or J-K inputs). Most flip-flops have other inputs that are asynchronous, meaning they affect the output independent of the clock. Two such inputs are normally labeled preset and clear. these inputs are usually active LOW.
The 74LS280 can generate even or odd parity. It can be used as ____________.
a parity tester
Parity generator/ checkers
an error detection method that uses an extra bit appended to a group of bits to force them to be either odd or even. In even parity, the total number of ones is ever; in odd parity the total number of ones is odd.
For transmission, data from a UART is sent in _______________.
asynchronous serial form
If the data select lines of the MUX are S1S0 = 11, the output will be _______.
equal to D3
The application illustrated is a ________.
frequency divider
The time interval illustrated is called ________.
hold time
An advantage of a ring counter over a Johnson counter is that the ring counter ___________________.
is self-decoding
D Flip-Flop
it does not have a toggle mode like the J-K flip flop, but it makes work as toggle by connecting NOT Q back to D
Schmitt trigger gates
it has two possible states just like other multivibrators. However, the trigger for this circuit to change states is the input voltage level, rather than a digital pulse. That is the output state depends on the input level, and will change only as the input crosses a pre-defined threshold.
Decoder
multiple-input multiple-output logic circuit that converts coded inputs into coded outputs, where the inputs and outputs coded are different.
Sequential circuit
output depends on present input and present state of the circuit (dependant on memory and uses a clock pulse)
Combinational logic circuit
output depends only on present input (dependant only on Boolean)
An S-R flip flop differs from an S-R latch because it has an ________________ .
pulse transition detector
If the SHIFT/LOAD line is HIGH, data __________.
shifted from left to right on the next CLK
What is happen when the open circuit in input/ output?
sometimes the very fine conducting wire that connects an IC pin to an ICs internal circuitry will break, producing an open circuit
Latches
temporary storage device that has two stable states (bistable). -Multivibrator The S-R latch is the most basic type, which can constructed from NOR gates or NAND gates. with NOR gates, the latch responds to active -HIGH inputs, with NAND gates, it responds to active-LOW inputs.
Set-up time (ts)
the logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry
Hold time (th)
the logic level must remain on the D input for a time qual to or greater than th after the triggering edge of the clock pulse for reliable data entry
Full adder
three binary inputs (A, B and Carry in) and two binary output ( Carry out and Sum)
Comparators
to compare the magnitudes of two binary numbers to determine the relationship between them. In the simplest form, a comparator can test for equality using XNOR gates. The lowest order comparator has a HIGH on the A=B input
For the J-K flip shown, the number of inputs that are asynchronous is _____.
two
Half adder
two binary inputs (A and B) and two binary outputs ( Carry out and Sum)
What is happen when the input/ output internally shorted to ground or supply voltage?
will cause the input/ output to be stuck in the LOW or HIGH state