EE234

Memory Stage

- Access data from memory/to memory - ALU will complete the instruction - Multiplication (16x32 multiplication will halt for 1 clock cycle, for 32x32 halt for two clock cycles) - Division will wait for up to 35 clock cycles - Branch and jump PC is updated - Bypass values to the execution stage

Alignment Stage

- Align the data - Division and multiplication is completed - Bypass the data to the execution unit

Priority Level

- Each request has an assigned priority level - PIC32 enables the developer to assign up to 7 priority levels such as leve 7 is the highest. - 4 sub priority levels may be assigned to events with the same priority levels. - If two or more requestes have the same priority and subpriority levels, the the natural priority decides where request to source first.

Load/ Store Instructions

- Load data from memory to GPR's - Store data from GPRs to memory

Interrupt Enable Control (IEC)

- Our board has IECO and IEC1. - Each interruptible module has a corresponding enable bit, such that the interrupt of that module will be triggered only if the enable bit is asserted high "1"

Interrupt Priority Control Registers (IPC)

- Out PIC 32 has 12 registers (IPC0 - IPC11) - Hold priority level (3 bits) and the sub-priority leve (2 bits) for each interruptible module. - IPC2 holds the priority levels for Timer 2 - All the information is available in the datasheet

Write Back to GPR

- Result is written back to GPRs

Execution Stage

- Start to execute the instructions - for ALU and DMU instruction the execution unit will move the operands from GPRs to ALU/DMU - Load/Store instructions, it will compute the virtual to physical Address - Branching/jump will calculate the new address and it will evaluate the testing conditions

Instruction Stage

- The execution unit will fetch the construction from memory - PC holds the address of the register to be fetched instruction

Interrupt Controller

- Used to break the flow of executing the software program based on some predetermined event. - Once the event is detected and one program stopped, it will execute a routine (interrupt service routine [ISR]). - Controls the interrupt event.

Interrupt Configuration Register (IntCON)

- interested in multivector enable bit - MVEC bit if MVEC = 1 the interrupt will use multivector interrupt else it will use single vector interrupt

Importance of a System Clock

- is to synchronize the overall system "core" - propagation delay is the limiting factor of overall clock speed

Interrupt Flag Status Register (IFS)

-When an interrupt of a particular module is active (CPU is serving), there will be a flag bit that is asserted "high", "1" for that particular module - each interrupt module has its own flag status bits - ISR must CLR "0" the flag status bit at the end of ISR.

Find the maximum value (assembly)

.ent Max Max: MOVE, $v0, $a0 SLT $t0, $a0, $a1 MOVEN $v0,$a1, $t0 jr $ra Nop .end Max

Return Minimum value of 100 words and start sequencing from the address start in $a0

.ent getMin getMin: #$t1 = min value LW $v0, 0($a0) #first value is minimum Addiu $s7, $a0, 396 Loop: Addiu $a0, $a0, 4 LW $t1, 0($a0) SLT $t2, $t1, $v0 MOVEN $v0, $t1, $t2 BNE $a0, $s7, loop # if $a0 != $s7, loop jr $ra Nop .end getMin

Interrupt Special Function Registers (SFRs)

1) INTCON = interrupt configuration *MVEC = Multivector Enable Control (if MVEC =0, use single vector interrupt. If MVEC =1, use multivector interrupt.)

Three types of instructions

1) Immediate Instructions - use Immediate value to execute the instruction. Format of immediate instructions: OPCODE (6bits), SOURCE GPR (5bits), DESTINATION GPR(5bits), IMMEDIATE VALUE(16bits). 2) Register Type Instruction - executes instructions of the GPR level. Format of register type instructions: OPCODE (6bits), SOURCE 1 GPR (5bits), SOURCE 2 GPR (5bits), SHIFT AMOUNT (5bits), SPECIAL FUNCTION (6bits) 3) Jump type instructions - are used for unconditional jump and branch. Format of jump type instructions: OPCODE (6bits), JUMP INDEX(26bits).

SFRS of interrupt

1) Interrupt Configuration Register (IntCON) 2)Interrupt Enable Control (IEC) 3) Interrupt Flag Status Register (IFS) 4) Interrupt Priority Control Registers (IPC)

Special registers

1) PC - Stores the address of next instruction 2) HI & LO - stores the high and low of a multiplication or division 3) Stack pointer - stores the address of the last program request in a stack

Features of CP0

1) System clock counter 2) Control interrupts and exceptions 3) Shadow register sets control (SRS = copies of GPRs) 4) Virtual Memory Configuration 5) Debugging Control 6) Performance Counter 7) Process Identification

Branch type instructions

1) They branch to a new address conditionally 2) They branch to in reference to a new address of the current instruction

Operation Modes of PIC32

1) User Mode - accessed by the user which has limited access to resources such as memory, configurations, debugging... 2) Kernel Mode - unlimited access to resources (memory, config, programming) 3) Debugging mode has limited access to all resources and extra features and extra debugging features.

Jump type instructions

1) they jump to a new instruction address unconditionally 2) they jump to the exact address

PIC32 has 5 stages

1- Instruction Stage 2- Execution Stage 3- Memory Stage 4- Align Stage 5- Write back to GPR

Microprocessor

A digital hardware module (system) that executes instructions. The module can be a complete integrated circuit (IC) or it can be a module within the integrated circuit.

PIC32 Microcontroller

A family of controllers that have same common basic features. They have different memory sizes and peripheral modules. They share the same core.

CoProcessor 0 (CP0)

A set of special register that are used by software to communicate & configure the core (CPU) MIPS32.

Basic Generic Microcontroller architecture

CPU core, control unit, peripherals, BUS, Memory, I/O

Architecture of MIPS32, core of PIC32

Co Processor, ALU, DMU, Execution Unit/Control Unit, EJTAG debugger, BUS, GPR, MMU (Memory Management Unit), memory interface, coprocessor, FMT, interrupt controller

PIC32 Microcontroller Architecture

Core MIPS32, JTAG Debugger, Interrupt, USB, CAN, Ethernet, BUS, Flash, Cache, RAM, Peripherals Bridge Matrix, Power Management, Control Unit, DAC, UART, SPI, I2C, ADC, IO, RST, Timers, RTCC, PWM, Input Capture.

EJTAG debugger

Debugging in real time which allows to halt instructions and evaluate the content within the internal modules.

DMU

Divide and Multiply Unit

Multivector Interrupt

Each event has a dedicated instruction address to serve the interrupt

PIC32 Interrupt Chip

Events ==> Interrupt Controller ==> Vector#, Priority Level, SRS# ==> Core CPU "MIPS 32" - each module has the ability to send an interrupt request to the interrupt controller based on same specific event.

ALU (Arithmetic Logic Unit)

Executes arithmetic operations such as add, sub, multiply. Executes logic operations such as and, shift, xor, etc.

Control Unit/ Execution Unit

Executes instructions/controls the operation

GPR

General Purpose Register

General Purpose Register (GPR)

High speed register that holds values

GPR Number 16-23

Name: $S0 - $S7, Functionality: Variables and constants within functions pressure values

GPR Number 30

Name: $S8, Functionality: Same as $S0-$7

GPR Number 4-7

Name: $a0 - $a3, Functionality: passing arguments to functions

GPR Number 1

Name: $at, Functionality: used by assembler as temporary

GPR Number 28

Name: $gp, Functionality: Point to memory location

GPR Number 26-27

Name: $k0 and $k1, Functionality: used kernel

GPR Number 2-3

Name: $r0 and $r1, Functionality: used for returned values of functions

GPR Number 31

Name: $ra, Functionality: Store the returned address

GPR Number 29

Name: $sp, Functionality: stack pointer (dynamic)

GPR Number 8-15

Name: $t0 - $t7, Functionality: Temporary register

GPR Number 24-25

Name: $t8 and $t9, Functionality: Temp. registers

GPR Number 0

Name: $zero, Functionality: hardwired to logic zero

RISC (Reduced Instructions Set Computer)

Small number of simple instructions

Co processor

Special registers are used by software to communicate & configure the core.

Interrupts

The break of the flow of executing the program, because of some triggering event. Then the core will execute a special function called interrupt service routine (ISR). Once completed it will go back to continue its execution of the software.

Bus

Transport or link digital data from one module to another

Shadow Register Sets

Used to copy GPRs before serving the interrupt service routine (ISR). - There are up to 16 SRS that can be assigned to different events - Interrupt controller decides to the core of which SRS to use for this requested interrupt. - The core receives the I.R. and decides which interrupt to serve. - If the core is serving an interrupt with a lower priority level than the new incoming interrupt request, the core will copy the GPRs into a designated SRS and serves the new interrupt request - Once the interrupt is served, SRS is copied back to the GPRs - The developer has the option to use the stack.

Single Vector Interrupt

Will point to a single instruction address to serve the interrupt

Generic Microcontroller

a complete module that contains a microprocessor w/ internal memory in addition to other modules. (peripherals)

Mnemonic

a method to make it easier to remember

Machine Language

a set of instructions that are executed in hardware and each instruction is coded as 0s and 1s using 32 bit instructions

I/O module

communicates with the external modules

Vector Number

each interrupt has an associated number which indicates the requested interrupt.

MMU (Memory Management Unit)

hardware module that is used to access data to/from external memory. It uses Fixed mapping translation (FMT) to access physical actual memory.

Memory interface Unit

interfaces with the external memory

Assembly language

is a set of instructions where each machine instruction has a mnemonic representation

Pipelining

to break down the execution of each assembly instruction into stages such that multiple consecutive instructions are executed in parallel so that the throughput is one complete instruction per clk cycle.

CISC (Complex Instructions Set Computer)

uses complex instructions that require complex hardware