EEL 4740 Final Exam Study Set

Which of the following VHDL operators has the highest precedence over the others. * + or sll

*

What is the size of counter that must be used to generate a 1 Hz clock signal from 12 KHz clock? 14 bit 12 bit 10 bit 8 bit

14 bit

According to Moore's Law, IC transistor capacity doubles every ---------------. 8 years 4 years 18 months 3 years

18 months

Using the revenue model presented in module 1, what is the percentage revenue loss if D = 2 and W = 10? 62% 45% 28% 16%

28%

What is the size of state register required for an FSM with 5 states? 2-bit 3-bit 4-bit 5-bit

3-bit

In the following entity what is the size of light_in vector? port ( lights_in : in std_logic_vector(0 to 3);lights_out : out std_logic ); 2-bit 3-bit 4-bit Not enough information

4-bit

Each product has a "market window". If the product is released on the market late in the window; there will be ---------- in revenues. An increase A loss A conflict A gain

A loss

A single-Purpose processor design can be optimized, by optimizing: Original program FSMD Datapath FSM All of the above

All of the above

In Moore FSM: desired output values are listed next to each state Input conditions that cause a transition from one state to another are shown next to each arc Each arc condition is ANDed with rising (or falling) clock edge all inputs are synchronous All of the above

All of the above

Which of the following is not a scalar data type? Integer Floating point Enumeration Array

Array

Which of the following is the criteria used to evaluate a processor's speed? Clock frequency Instructions per second Benchmark results Manufacturing technology

Benchmark results

Look-up table (LUT) is a part of -------------? Fuses CLB Interconnections (I/O) blocks

CLB

A controller consists of a state register and a ------------------------logic block. Control Combinational Sequential Programmable

Combinational

What part of a controller provides for the next state and output logic? State register FSM black-box Output signals Combinational logic block

Combinational logic block

Match the type of VHDL object with its description. Constant Variable Signal Declared in architecture and used anywhere within the architecture Can only hold a single value that cannot be changed Used in the processes and subprograms

Constant - Can only hold a single value that cannot be changed Variable - Used in the processes and subprograms Signal - Ddeclared in architecture and used anywhere within the architecture

What is the issue associated with the usage of push buttons that can result in false triggering? Contact debounce Single pole single throw Slow response time No latching

Contact debounce

Which microcontroller is a better choice for a digital camera, considering that pictures must be transferred to a computer? TI C5416 16 bit, 160 MHz, SRAM, DMA, 13 ADC, 9 DAC Cortex-A9 32 bit, 800 MHz, Neon coprocessor, L1, L2 cache Intel 8051 4K ROM, 128 RAM, 32 I/O, Timer, UART Motorola 68HC11 4K ROM, 192 RAM, 32 I/O, SPI, WDT

Cortex-A9

What can be used for frequency division and slowing down the clock frequency? Delay circuit Timer Register Counter

Counter

Match the VHDL model type with its description. Data Flow Behavioral Structural May contain Process statements Used for connection of sub modules Concurrent execution.

Data Flow - Concurrent execution. Behavioral - May contain Process statements Structural - Used for connection of sub modules

-------------- stores and manipulates a system's data. Register Controller Datapath RAM

Datapath

In the following VHDL statement "after" clause is used to indicate a -----------. Y <= not a after 1 ns; Sequence State Delay Time period

Delay

When modeling FSM in VHDL, a (an) ----------------- type can be used for the states: Class New Enumeration Signal

Enumeration

To implement the same functionality which IC technology will have the largest size? VLSI ASIC FPGA

FPGA

A given ASIC design can be used for any embedded application. True or False?

False

An embedded system always requires an operating system. True False

False

Cross compiler runs and generates code on the same processor True False

False

Generally an embedded design metric can be improved without affecting others. True or False?

False

SRAM based FPGAs with on-board memory are not reprogrammable. True or False?

False

Which of the following is not a basic element of FPGA? Fuses CLB Interconnections (I/O) blocks

Fuses

Which processor has low NRE cost, short time-to-market/prototype, high flexibility? Custom Single-purpose processor Single-purpose processor Application-specific processor General purpose processor

General purpose processor

Which processor has low NRE cost, short time-to-market/prototype, high flexibility? Custom Single-purpose processor Single-purpose processor Application-specific processor General-purpose processor

General-Purpose Processor

The complex state diagram called finite state machine with data, FSMD is used for the design of custom single-purpose processors. FSMD is also referred to as ------------- . HLSM FSM LSM MLS

HLSM

Which of the following is not an FPGA application? IPAD CPU Image processing and enhancements CPU accelerators ASIC emulation verification

IPAD CPU

The number of clock cycles needed to complete one instruction is called: Instruction cycle Processor performance Clock cycle Frequency

Instruction cycle

What is not a characteristic of I2C bus? It has three wires one for data and two for control. It is a serial transfer standard. Each servant has a unique address Microcontroller is the master.

It has three wires one for data and two for control.

Which of the followings can be used to minimize the logic and make Boolean equations simple? LUT CLB K-map FSM

K-map

Which of the following is not an embedded system? Digital Television Laptop Digital Camera Anti-lock brakes system in a car

Laptop

For ------------- FSM output depends both on current state and inputs. Moore Mealy Controller Sequential

Mealy

Which of the following is not a standard peripheral? Timer/Counters Stepper motor driver Microcontroller LCD controller

Microcontroller

For ------------- FSM output depends only on current state. Moore Mealy Controller Sequential

Moore

In which state machine output signals are synchronized with the clock? FSM HLSM Mealy Moore

Moore

Which of the following is not a common characteristic of embedded system? Single functioned Real-time Low Power No Cost Limit

No Cost Limit

What is the most important feature of a processor to control a pacemaker that must be implanted in the patient's body? Safety Size Power Consumption Cost

Safety

A --------------- circuit is a digital circuit whose outputs are a function of the present as well as the previous input values. Combinational Digital Sequential Analog

Sequential

-------------- is an integrated circuit that integrates all components of an embedded system into a single chip. General Purpose Processor PLD FPGA SoC

SoC

-------------- is an integrated circuit that integrates all components of an embedded system into a single chip. General purpose processor PLD FPGA SoC

SoC

VHDL code has three parts. Which of the following is not part of VHDL code? Test bench Library Entity Architecture

Test bench

In FSMD, states and arcs may include arithmetic expressions. True or False?

True

In VHDL , signals are used to represent internal variables that are not the module input or output like: signal p, g: STD_LOGIC; True or False?

True

UART is asynchronous because the clock information is not sent. True False

True

Which peripheral converts serial data to parallel and vice versa? SPI I2C ADC UART

UART

---------- cost is the monetary cost of manufacturing each copy of the system. Total NRE Unit Product

Unit

Which IC technology has the highest NRE? VLSI ASIC FPGA

VLSI

Which IC technology provides the best size, power, performance? VLSI ASIC FPGA PLD

VLSI

In A VHDL process statement for a flip-flop, a ------------ "reset" must be included in the sensitivity list. asynchronous synchronous rising-edge triggered active-low

asynchronous

Register Transfer (RT) is a ---------- level of abstraction than logic gates, since it used for flow of digital signals between registers. same higher none of these answers lower

higher

Which VHDL library must be used for integer arithmetic operations? ieee.std_logic_1164.all; ieee.std_logic_textio.all; ieee.numeric_std.all; ieee.math_complex.all;

ieee.numeric_std.all;

In VHDL, which of the following statements are used to synchronize with the falling edge of the clock?(select all that apply) if( clk = '0' and clk' event ) then if (clk = '0' and clk_edge) then if falling_edge(clk) then if not(rising_edge(clk)) then

if falling_edge(clk) then if( clk = '0' and clk' event ) then

Which of the following VHDL statements must be used to turn on an active-low output? output <= '0'; output <= '1'; lamp_lit_N <= 'zzzzzz';

output <= '0';

In VHDL a ----------------- statement with a sensitivity list is used for sequential logic. statetype process behavioral structural

process

VHDL if statement is an example of a ------------- statement. It is a conditional statement which uses boolean conditions to determine which blocks of VHDL code to execute. combinational sequential synchronous asynchronous

sequential