hardware ch 3

A-series AMD supports this, a combination of CPU and GPU in the same processor housing unit

Accelerated Processing Unit

This is when you can set the order in which the system tries to boot from certain devices called boot sequence or

Boot priority

Released in 2015, little faster than Haswell and compatible with the LGA1150 socket

Broadwell

This system of pathways used for communication and the protocol and methods used for transmission are collectivelly called the

Bus

AMD and Intel are 2 separate

Chipset

Doing this to the TPM chip will erase encryption key, and data will be lost too

Clearing it

UEFI can backward compatible with MBR using (spell it out)

Compatibility support module

The bus/core ratio in a clock speed is also called the

Core Max Multiplier

To get the frequency of the processor, you multiply 100 MHz by the

Core Max Multiplier

Hub architecture, North Bridge contains graphics, memory, controller and connects directly to processor by way of 64-bit bus called

Front side bus

Method of portioning the drive, up to 128 of them, required for drives larger than 2 TB or systems using UEFI firmware (spell it out)

GUID Partition Table

This intel chipset, 2013, work with the LGA1150, LGA2011 sockets DDR3, DDR4 memory and less power than ivy bridge.

Haswell

Speed of memory, front side bus, processor is measured in

Hertz

Basic system clock provided by the chipset by which all other components synchronize activities.

Host clock frequency

This Intel chipset architecture has a hub used to connect 2 buses. This hub has a fast and slow end, and each end is a separate chip on mobo. What architecture ?

Hub

Mini-ITX is also called an

ITX board

The first PCI bus had 32-bit data path, supplied 5V of power to an adapter card and operated at this speed (first bus that allowed adapter cards to run in sync with the cpu)

33 MHz

Data path size are 8, 16, 32, __, 128

64

PCI-X has slots with different speeds, a 32-bit and a ___ slot running at different speeds

64-bit

PCI ended up with 4 types of slots. 2 sizes. 32-bit PCI and

64-bit PCI-X

UEFI required for OS later than _____and for drives larger than ____

8, 2TB

These chipsets are designed to support AMD processors the can have up to 8 cores.

9-series chipset

The 2 current chipset families by AMD are:

9-series, A-series

In a motherboard, some devices work to the beat of this (sometimes the cpu, do 2 operations per beat)

clock

This on motherboard used to enable, disable a port or component, control frequency of CPU, security features and what happens when PC first boots

firmware

If a connector in a motherboard is a group of pins sticking up on the board, the connector is called a

header

3 most popular form factors for motherboards, are ATX, microATX and

mini-ITX

Hertz and Gigahertz is measured in cycles per

second

PCI-X is backwards compatible, besides 5-V, and mostly used in

servers

This size PCIe, has single lane for data = 4 wires, one pair t send data and other to receive data one bit at a time.

x1

PCie has 4 different sizes

x1, x4, x8. x16

UEFI has mouse enabled interface (unlike BIOS) yes or no?

yes

A motherboard might have these connected on the inside of the case, including SATA, USB, and FireWIre

Internal connectors

Third generation processor and chipsets by intel, 2012, uses less power, squeeze more transistors into smaller space and better than earlier products

Ivy bridge

This is 2 small posts or metal pins that stick up on mobo that has config info. You can use this to clear BIOS/UEFI settings to default, clear settings or forgotten password

Jumper

Database that holds digital signatures provided by OS manufacturers. (KEK)

Key exchange key

Sandy bridge processors uses the LGA1155 socket or the

LGA2011

The first LGA socket was the (which had 775 pins)

LGA775

This method of processors contacts has blunt protruding pins on socket that connects with lands or pads on bottom of processor

Land grid array

Local buses run in sync with the system clock, local buses that connect to the slower I/O controller (south bridge) hub is called the

Local I/O bus

Video cards uses buses that uses PCIe x16 slots connect to north bridge or processors called

Local video bus

Embedded tech in laptops that protects against theft, locate when connect in internet, give commands through internet to lock and delete data.

Lojack

Old method of partitioning the drive, allows 4 partitions and limited to 2Tb drives. (Spell it out)

Master Boot Record

A bus can also carry electrical power, control signals, and

Memory addresses

This method of processors contacts is the sockets having holes aligned in uniform rows around socket to receive pins from the processor

Pin grid array

Digital signature belonging to mobo or computer manufacturer, (PK) authorizes turning on or off secure boot and updating the KEK database

Platform Key

In Sandy bridge, in leu of the north bridge and the south bridge only 1 chipset housing is needed called the

Platform controller hub

In the sandy bridge chipset, Usb 2.0, ethernet, HD audio, PCIe v2.0, SATA, eSATA connects directly to the

Platform controller hub

The ivy bridge chipset, uses LGA1155 socket and uses a single chipset hub called the

Platform controller hub

In the Nehalem chipset, the 64-bit front side bus was replace with technology called the

Quickpath interconenct

Blacklist of signatures for software that has been revoked and no longer trusted (dbx)

Revoked signature database

You are installing a MicroATX and slim case does not have enough room for PCI card to stand up in an expansion card, you use this to provide slot at a right angle.

Riser card

This architecture, when PCIe v2.0 graphics, could be dual cards, and DDR3 connects directly to the processor by intel. (Much faster)

Sandy Bridge

2011, intel chipset architecture which memory and graphics controller is in the processor. And instead of north and south bridge, only 1 chipset housing is needed

Sandy bridge

UEFI has this that prevents a system from booting up drivers or OS that are not digitally signed or trusted by mobo or manufacturer.

Secure boot

Ethernet, USB, firewire uses this bus

Serial bus

PCI uses a 32 and 64-bit parallel bus, PCIe uses this (much faster!)

Serial bus

List of digital signatures approved by OS, apps, and drivers that can be loaded by UEFI (db)

Signature database

In a hub architecture, all PCie slots besides video card must access in which bridge?

South bridge

This end of the hub architecture, has I/O controller hub, all I/o devices except video, connected to this hub by using slower

South bridge

Another word fro Front side Bus is called ____ or host bus

System bus

Line on a bus dedicated to timing the activities n the mobo like a metronome.

System clock

Chip in computers that work with bitlocker encryption (or other software like it) which the chip holds the bitcloker encryption key (aka the startup key)

TPM chip

Lines in a motherboard on both top and bottom of board surface. Circuits or paths that enable data, instructions, and power to move from component to component on the board.

Traces

If BIOS update fails, you need to revert back to earlier version by DL recovery file into a ___, then set the ___ on mobo, ___ system, and then perform the recovery.

USB, jumpers, reboot

PCI has 6 different cards (2 sizes). A 3.3V, 5V, and both voltages in one called ____ 3.3V or 5V.

Universal

To maintain a motherboard, you must ____ mobo drivers, ___ BIOS/UEF, ___ the CMOS.

Update, flash, replace

Nehalem Chipsets support LGA1366 socket, i7 processor, PCIe v.2 and can support either SLI and CrossFire technologies. (These allow for multiple ___ installed in one system)

Video cards

One component wants to write data to another, they get in sync for the write operation. The first component, places this on several lines of the bus. Other reads it. CPU and other devices, interpret this and lack f this as binary

Voltage

If HDD is stolen and put in another motherboard, TPM chip restricts access. But if mobo fails you would need a

Backup copy

This method of processors contacts is not really a socket but soldered to the motherboard, both always purchased as a unit.

Ball grid array

This method of processors contacts has the chip flipped over so that the top of it is on the bottom and makes contact with the socket. Not compatible with FCPGA.

Flip chip land grid array

Fast end of the hub architecture is the

North bridge

Mini PCie has 52 or 54 pins on edge connector and has this on center of slot. (Mini PCI wider 100 or 124 pins)

Notch

Version of PCie allowed for 150 W. Pins on expansion card and 6-pin PCie provides additional 75 W

1.0

Version of PCi allowed wattage of PCIe cards up to 225 W.

1.1

The QPI (QuickPath interconnect) works similar to how PCIe works with this amount of lanes for data packets.

16 lanes

PCI version Double of 1.0, allows for up to 32 lanes on one slot. Allowed on one set up to 300 W by using 8-pin PCie over connector that provides 150W.

2.0

This version of PCI, introduced 64-bit, 3.3-V (adding a notch to differentiate)

2.0

PCI version double of 2.0, backward compatible with 2.0.

3.0

Intrusion-detection (not recommended for being annoying) can be tripped from a failed

CMOS

Process of upgrading or refreshing programming stored on firmware chip is called

Flashing bios

Part of the bus with the lines of the bus that are used for data called the

Data bus

Width of the data bus is called the

Data path size

Small programs stored on HDD that an OS uses to communicate with a specific hardware device.

Device drivers

For every 8 bits of a bus, a bus MIGHT use a 9th bit for

Error checking

Chipsets that uses a south bridge always connects to this bus

Expansion bus

This bus does not run in sync with the system clock

Expansion bus

DL updated file to HDD in OS and you can update firmware chip from there, method:

Express BIOS update

This is the original version of UEFI is (spell it out)

Extensible Firmware Interface

You can update a firmware via USB, with a copy, by restarting it and pressing

F7

Mini PCI smaller form factor of PCI and the smaller version of PCIe is

Mini PCIe

Today processors go in sockets, but they used to go in

Narrow slots

Starting with the X58 chipset, 2008, the memory controller is contained in the processor housing. Directly connected to it rather than the north bridge

Nehalem chipset

You install the I/O shield in a motherboard AFTER installing it on the computer? Yes or no?

No

Another word for integrated components in a motherboard is called

Onboard ports

UEFI drivers, like keyboard, mouse, required as computer boots, digitally signed and ID by signature database

Option ROMs

After PCI, this came out, 64-bit data path and had 3 revisions, last being 3.0

PCI-X

Replaces PCI and PCI-X and not backward compatible with these

PCie

In the hub architecture, the video card has direct access to the north bridge via

PCie slot

AMD has chosen to use this socket architecture. (Although some AMD server processors use socket F, an LGA socket)

PGA

Another name for Nehalem chipset is the (also named for the north bridge)

X58 chipset

Can a short PCie card (x1) be installed in a x4 slot? Yes/no

Yes

Processors need even force applied when insertion, all current sockets have 1 or 2 levers on side called this. Also used to lift processor up and out of it.

Zero insertion force sockets