Sequential Logic

What is an asynchronous input in a FF?

An input that has an effect independently of any clock or enable inputs e.g. Reset/Clear, Preset/Set

What do flip flops often have as well as clock and enable inputs?

Asynchronous inputs

Finite State Machine

Deterministic machine that produces outputs which depend on its internal state ad external inputs

Inputs

External stimuli, labelled as arcs on the state diagram

Describe FPGA devices

Field Programmable Gate Array devices, lots of programmable wiring and function blocks controlled by bits downloaded from memory, function units contain a 4-input 1 output look-up table with an optional D-FF on the output

What does the asynchronous input Reset/Clear do?

Force Q to 0

What does the asynchronous input Preset/Set do?

Force Q to 1

Setup time in a timing diagram

Minimum duration that the data must be stable at the input before the clock edge

What is a GAL (Generic Array Logic)?

Modified PALs which can use D-type FFs in the OR plane (one following each OR gate) and the outputs from the D-types are directed to the the AND planes in addition to the usual inputs to be used if needed.

Outputs

Results from the FSM (Finite State Machine)

For a FF to operate properly, what two timings need to be satisfied?

Setup time (i.e. input must not change before clock edge) and hold time (i.e. input must not change after clock edge)

Hold time in a timing diagram

The minimum duration that the data must remain stable on the FF input after the clock edge

What is the setup time for a flipflop?

The minimum time for which the data must be stable at the input before the clock edge

What is the hold time for a flip flip?

The minimum time for which the data must remain stable on the FF input after the clock edge

Propogation delay

Time from application of active clock edge to valid data at the Q output

What is a sequential circuit?

When the output is fed back into the inputs for the circuit

What is a synchronous circuit?

When the output of a sequential circuit is only allowed to change at a time specified by a global enabling signal i.e. the clock

States

Set of internal memorised values, shown as circles on the state diagram