VHDL

Component declarations

-- RGB driver component RGB_Driver Port ( Buttons : in std_logic_vector (1 downto 0); RGB_out : out std_logic_vector (0 to 2)); end component; A component declaration declares a virtual design entity interface that may be used in component INSTATIATION statement can be INSTATIATED IN ANOTHER ARCHITECTURE leading to hierarchical specification. component must be DECLARED before it is INSTATIATED

Component instantiations

-- component instantiations i_RGB4_Driver: RGB_Driver port map ( Buttons => btn(1 downto 0), RGB_Out => RGB_Led_4 );

NAND

0 NAND 0 is 1 0 NAND 1 is 1 1 NAND 0 is 1 1 NAND 1 is 0

NOR

0 NOR 0 is 1 0 NOR 1 is 0 1 NOR 0 is 0 1 NOR 1 is 0

XNOR

0 XNOR 0 is 1 0 XNOR 1 is 0 1 XNOR 0 is 0 1 XNOR 1 is 1

XOR

0 XOR 0 is 0 0 XOR 1 is 1 1 XOR 0 is 1 1 XOR 1 is 0

Concatenation

1 way to combine 'bits' to 'arrays' b_bus <= x & "00" & w;

D Flip-Flop

A flip-flop with one data input that stores the value of that input signal in the internal memory when the clock edge occurs D is sampled on a rising edge of CLK signal D is copied to Q The output state is maintained until the next rising edge of the clock single bit memory cascading them by connecting Q' to CLK of next registers you can create mod4 counter etc.

Named association

A form of AGGREGATION which is a way to combine 'bits' to 'arrays' b_bus <= (2=>x,1=>y,3=>z,0=>d);

Positional association

A form of AGGREGATION which is a way to combine 'bits' to 'arrays' b_bus <= (x,y,z,d);

PWM Rate / Switching frequency

A parameter to define operation of a PWM Defines PWM cycles/time unit

PWM resolution

A parameter to define operation of a PWM: How many discrete steps you have from zero output (power) to full output (power)

Mealy

A type of FSM where The outputs depend on current state AND inputs

Moore

A type of FSM where The outputs depend only on current state

Indexing

Accessing a "slice" of an array The direction of the slice (i.e. to or downto) must match the direction in which the array is declared signal z_bus: std_logic_vector(3 downto 0); signal a_bus: std_logic_vector (1 to 4); a_bus <= z_bus; -- ok z_bus(3 downto 2) <= "00"; --ok a_bus(2 to 4) <= z_bus(3 downto 1); --ok z_bus(2 to 3) <= "00"; -- NOT OK

ASIC

Application Specific Integrated Circuit Design starts with an empty silicon, where everything needs to be designed • Typically, standard cell libraries are used • No need to put anything extra, so it is fully optimized ans can be designed for extreme performance, low power or low price (or even all of them at the same time) • Design work is _really_ expensive to design (Tools, NRE costs), but cheap in high volumes

Why NAND/NOR-gates are favored in actual implementations?

Because they require 2 (CMOS) transistors less than AND/OR

Synchronous Counter

Counter in which all of the flip-flops are clocked simultaneously. Use T flip flop: output toggles (changes state) on clock edge IF the input T is '1'- otherwise no change D flip flops can be converted to T flip flop Cascading T flip flops gives you a synchronous (BCD) counter

DEMUX

Demultiplexer Maps "one input to one of many outputs"

FPGA

Field Programmable Gate Array • A ready made "canvas" with logic gates, registers, memory elements etc and the it is "just missing the interconnections". Programming an FPGA means programming the interconnections (a bit simplified view...) • Quite expensive, especially the big and fast ones • There is always extra, unused logic, so utilization is not 100% • Higher power consumption than ASICs • Due to programmability, very flexible: you can download hardware updates

Elaborate

First step used by synthesis tool that translates the textual design to a netlist of technology primitives (ANDs, ORs, Multiplexers... and in case of FPGAs, Look-Up-Tables (LUT))

HLS

High Level Synthesis, or C synthesis or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates digital hardware that implements that behavior. Can be done with SystemC

MUX

Multiplexer Selects "one input of many" to single output

Delay statement

Non synthesizable vhdl command used in TB r_Enable <= '0'; wait for 100 ns; r_Enable <= '1';

File/Text I/O

Non synthesizable vhdl command/function used in TB

Assertion

Non synthesizable vhdl command/function used in TB assert (A and B = 0) report "A and B simultaneously zero" severity warning;

PWM

PWM is a component (or a modulation method), which alters the ratio between "on-time" and "off-time" of a signal. This ratio is also called duty cycle average value tells how much power is transferred to the load during a cycle

RTL

Register Transfer Level is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals VHDL and Verilog are for RTL Synthesis

VHDL

Very High Speed Integrated Circuit Hardware Description Language.

Conditional Signal Assignment

Y <= A when (s = "00") else B when (s = "01") else...

Finite State Machine

a machine that consists of a fixed set of possible states with a set of allowable inputs that change the state and a set of possible outcomes when making VHDL presentation of FSM, you need to decide: • The description style - how many processes? • Encoding of states (synthesis can do this automatically)

generic

c is a parameter- or a "specification", which value is evaluated during compilation/synthesis NOTE: it does not "change" your block run-time Generics are listed in entity, before port list. Similarly, component needs to have a generic list as well, as it represents the "interface" of an entity entity entity_name is generic (generic list); port (port list); end entity_name; component component_name generic (generic_list); port (port_list); end component; instance_label: component_name generic map (generic_association_list) port map (port_association_list);

Array

contains multiple elements of same type type MY_BUS is array (3 downto 0) of std_logic_vector(15 downto 0); type RAM is array (0 to 31) of integer range 0 to 255; signal A_BUS : MY_BUS; signal RAM_0 : RAM;

modulo n counter n = 2^x (async)

counter wraps over if not reset condition is required has timing problem because if you have long ripple counter it takes time for all bits to change limiting the clock speed

Steps of logic synthesis

elaborate, optimization, netlist, implemented

Logic Synthesis

is the process of converting a high-level description of design into an optimized gatelevel representation. • Logic synthesis for ASIC designs uses a standard cell library which have simple cells, such as basic logic gates like and, or, and nor, or macro cells, such as adder, muxes, memory, and flip-flops. • Standard cells put together are called technology library. Normally the technology library is known by the transistor size (0.18u, 90nm,65nm ... 12nm end even below)

Concurrent statements

led4_r <= RGB_Led_4(2); led4_g <= RGB_Led_4(1);

Netlist

list of elementary building blocks to be implemented on silicon

Sequential Logic Circuits

outputs are dependant on both their present inputs and their previous output state giving them some form of Memory

Combinational Logic Circuits

outputs are only determined by the logical function of their current input state, logic "0" or logic "1" at any given instant in time they have no feedback, any changes to the signals being applied to their inputs will immediately have an effect at the output. output is dependent at a ll times on the combination of its inputs, it is memoryless

Entity

part of VHDL program structure that contains Generics and Ports

Architecture

part of VHDL program structure that contains component declarations, signal declarations, component instantiations, concurrent statements, processes architecture rtl of led_thing is .. ..

Implemented

place and route

State Machine

sequential design unit with a "memory" - representing the current state of the machine

Signal declarations

signal RGB_Led_4: std_logic_vector(0 to 2);

Optimization

synthesis/optimization is driven by constraints : time, area (usage of resources) or power

Test Bench

top level design unit for simulation only contains: Instatiation of Device Under Test (DUT) Stimulus signals for DUT (generators for input waveforms, clock driver, reset etc) • (Optionally) generation of reference outputs and comparison to DUT outputs Can provide automatically a pass or fail indication

Selective Signal Assignment

with s select Y <= D0 when "00", D1 when "01", D2 when "10", D3 when others;

Zynq7000 (7z020) has 13300 logic slices, each containing

• 4 6-input LUTs (with 64x1- bit memory capability) • 8 flip-flops (Register and shift register functionality) • Cascadable adders

Xilinx Zynq-7000

• A family of SoC-FPGAs, integrating one or more ARM A9 processor cores and Artix-7 (or Kintek-7) programmable FPGA logic fabric