chapter two computer architecture part two
what are current issues with memory?
-CPUs are faster than memories. - on a read: the slower the memory. the greater number of cycles will have to wait. -fast memory is very expensive, slow is cheap. -lots of memory is: BIG; limited chip size.
what does secondary memory consist of?
-RAM -Hard disk
what are cache design issues?
-cache size: bigger cache = bigger cost -cache organization: how to determine which memory cells are in the cache. -unified/split cache: instructions/data: keep both in one cache, or separate caches.
what are characteristics for primary memory?
-fast -small -expensive -closest to CPU
what does primary memory consist of?
-registers -level 1 and 2 cache
what are two primary methods for data parallel computers?
1. SIMD processors 2. vector processors
what are the pipelining steps?
1. instruction fetch 2. instruction decoded and register fetch 3. execute 4. memory access 5. register write back
what is the computer equation?
CPU + memory + I/O
what is major difference between SIMD processor and Vector processor?
SIMD processor is considered as of a parallel computer, but vector processor is considered as of single computer.
what is a SIMD processor?
a single instruction-stream multiple data stream of a large number of identical processors that performs same sequence of instructions on different sets of data.
what is instruction pipelining?
instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. pipelining attempts to keep every part of the processor busy with some instruction.
what is instruction level parallelism?
instruction-level parallelism (ILP) is a measure of how many of the instructions in a computer program can be executed simultaneously (at the same time).
what is a vector processor?
it appears to the programmer very much like a SIMD processor. like a simd processor, it is very efficient at executing a sequence of operations on pairs of data elements.
using the three variable multiplexer chip of fig. 3-12 implement a function whose output is the parity of the inputs, that is, the output is 1 if and only if an even number of inputs are 1
just add the inputs and the result (the least significant digit) is the answer you need. 0 + 0 + 0 = 0 0 + 1 + 0 = 1 + 0 + 0 = 0 + 0 + 1 = 1 1 + 1 + 0 = 0 + 1 + 1 = 1 + 0 + 1 = 10 -> 0 1+ 1 + 1 = 11 > 1
what is k in memory?
k = log2(m) address input signals or m = 2^k cells
What is the memory units: m X n
m cells of n bits each
there exit four boolean functions of a single variable and 16 functions of two variables. how many functions of three variables are there? of n variables?
n ^n, n ^ 2n, n ^ n^2 and 2 ^ n^2
there exist four boolean functions of a single variable and 16 functions of two variables. how many functions of four variables are there?
n, 36, n - (2n) ^2
what is the first initial of using pipelining?
single and dual pipelining were originally used on RISC machines = Intel 486 but 386 didn't have any.
why problem led to superscalar architecture and what does it look like?
the idea of adding more than dual pipelining needs more hardware and they decided to have one single pipelining with multiple functions = Intel . They have one single pipelining but many functions.
