COE121 FINALS (ISAGANI) MCQ COMPILATION

2nd

.Transistors are of _____ generation of microprocessors

History bits

Branch prediction is assisted by the use of:

Register

It is a temporary storage of information inside the CPU

Intel

Robert Noyce and Gordon Moore were the co-founders of

Pentium 4

Which CPU supports RAMBUS memory technology

Pentium, Pentium MMX, Celeron

Which has no L2 cache?

CMPXCHG

Which instruction is NOT new Pentium instructions?

56

"A doubleword number, 12345678H, is to be stored into memory using little endian format starting at memory location 00100H. What would be the content of memory location 00101H?"

34

"A doubleword number, 12345678H, is to be stored into memory using little endian format starting at memory location 00100H. What would be the content of memory location 00103H?"

little endian ; big endian

"Intel CPUs are also called _____ computers, while Motorola processors are called _____ computers."

BUSICOM

. The project that produced the first microprocessor originated in 1969 and was conceptualized by the company

Double-Word

.32-bit binary numbers are referred to as _____.

OF=0; IF=0; ZF=0; AF=1; PF=0; CF=0

.Given the initial statuses of FLAGS - OF=0; IF=1; ZF=0; AF=0; PF=? and CF=0 and that AL=FF and BL=01. Simulate the following instructions to determine the final statuses of the FLAGS: ADD AL, BL CLC CLI

BRDY#

.Indicates that a new valid bus cycle is currently being driven by the Pentium processo

Burst operation

.It allows a new 8-byte chunk to transfer every clock cycle

Trap Flag (TF)

.It is a type of flag register that provides single-step capability for debugging.

They should only contain segment addresses

.One must never use the segment registers as data registers to hold arbitrary values because:

Pentium Pro

0.Separation of I- and D-caches is first implemented in

1 MB

16-bit 8086 and 8088 microprocessors can access _____ of memory

16 MB

80286 microprocessor is very similar to 8086 and 8088 except that it can access _____ of memory.

1, 0

A Trap Flag enables trapping through an on-chip debugging feature. If T=_____, it will debug. If T=_____, it will not debug."

20-bit

A processor running in real-mode is limited to use _____ of its address bus to access the memory system

Pentium Overdrive

All of the following Pentiums has 64-bit data bus except

Pentium Pro

All of the following belongs to P6 microarchitecture family except

Second Level cache

Also known as an external cache

Immediate addressing

An addressing form in which the data to be used or retrieved in the instruction, is located immediately after the opcode of the instruction.

MOV SI,[BX+04]

An example of register-relative addressing mode

HOLD

Bus _____ input provides a second way for a different bus master to take control of the Pentium's buses.

RISC

Choosing to make the instruction set smaller using fewer instructions and simpler addressing codes was the decision of _____ designers.

Vacuum tubes

Electronic Numerical Integrator and Computer were built using _____.

Intel 8080

First chip developed by Intel

21000H

Given CS = 2000H and IP = 1000H, find the memory address of the next instruction executed by the microprocessor.

OF=1; ZF=1; AF=1; PF=1; CF=1

Given the initial statuses of FLAGS - OF=0; ZF=1; AF=0; PF=1 and CF=0 and that AL=1F and BL=F1. Simulate the following instructions to determine the final statuses of the FLAGS: ADD AL, BL

Writes byte of data from BH into memory location 1000H

If SI = 1000H, what does MOV [SI],BH do?

Shutdown

If an internal parity error is detected by the Pentium, a _____ cycle is run

State 2, State 3

In the Branch Prediction, which states predict a jump?

Register relative addressing mode

In this addressing mode, the data in a segment of memory are addressed by adding the displacement to the contents of a base or an index register (BP, BX, DI, or SI)

HIT#

Indicates to the Pentium whether or not the system can support a cache line fill for the current cycle

BIU

It controls the access to the system buses by generating memory address and control signals, and passes and fetches data or instructions to either a level 1 data cache or a level 1 instruction cache

Cache

It is a special type of high speed RAM where data and the address of the data are stored.

Pipelining

It is a technique used to enable one instruction to complete with each clock cycle.

Little endian

It is the way where the higher byte is stored in the higher memory.

BOFF

It provides a way for other processors in a multiprocessor system to instantly take over the Pentium's buses.

NVM

Its function is for floating point, graphics, signal or string processing, and even encryption.

Integer data, floating point number

MMX instructions can process

Base-plus-index

MOV AX,[BX+4] is a sample of which type of addressing?

Execute

Memory is sometimes accessed, I/O devices are used to display the result of the instruction execution.

3

Pentium Pro's IFDU contains how many separate instruction decoders for simultaneous decoding

2

Pentium can run _____ instructions concurrently

Superscalar

Processors capable of parallel execution of multiple instructions are called _____ machines.

Pentium 4

SSE2 is first introduced in

A global descriptor table

TI = 0 indicates that TI is _____

It is available on a plug-in cartridge

The Pentium II differs from earlier microprocessors because

Conventional, real mode

The first 1Mbyte of memory is called the _____ memory system

VM

The following are new flags bits made available in Pentiums except for

Pentium

The following microprocessors are all 3-way superscalar except

Has mixed sizes operands

The instruction MOV DS:[2000H], AL

Jack Kilby William Shockley

The invention of Integrated Circuit (IC) was credited to

16 bytes

The minimum distance possible between two overlapping 64-kB memory segments is

CPU, memory, I/O, system bus

The most basic but complete microprocessor-based computer would consist of

1, 0

The parity flag was used in early Intel microprocessors for error detection of transmitted data. PF is logic _____ for odd parity and a logic _____ for even parity

AE98D

The physical address accessed by segment offset combination A359:B3FD

Cache hit

The state in which data requested for processing by a component or application is found in the cache memory?

8008

The world's first 8-bit microprocessor

True

There were already commercial computers developed and sold even before the IC was invented

Executive Engine Line

These are all component of NetBurst Architecture EXCEPT

Interrupt

These are signals that indicate need of attention, perform special task and resume the pre-empted operation.

APCHK

This Pentium signal provides even parity for the memory address on all Pentium initiated memory and I/O transfers.

Indirect

This addressing mode uses a register to hold the actual address that identifies either the source or the destination to be used in the data move.

Single-transfer

This cycle is used to transfer up to 8 bytes of non-cacheable data between the processor and memory

Read after write

This data dependency exists if the second instruction reads an operand written to it by the first instruction

Program Counter

This element is always in phase with the clock system of the microprocessor

Watchdog monitor

This element is the one responsible in monitoring the bus operation

I/O port

This element serves as a medium of communication between the processor and the outside world

System bus

This is a group of lines that has a related function within a microprocessor system.

MOV AX,[BX]

This is an example of Register Indirect Addressing Mode

Pipelining

This is an implementation technique where multiple instructions are overlapped in execution?

Instruction register

This register works very closely with the instruction decoder of the control unit and stores all instructions coming from the data bus.

FLUSH

This signal causes the Pentium to writeback all modified data lines in its internal code and data cache

Hit ratio

This specifies the percentage of hits to total cache accesses.

Real, Protected and Flat mode

What are the three kinds of processor modes or CPU modes.

4455FH

What is the ending address of a memory segment if the segment register contains 3456H?

Lack Dependencies, Basic, Contain no displacement

When two instructions are to be pair, it must

Direct, Immediate

Which addressing mode executes its instruction within CPU without the need to access the memory

Direction Flag

Which among the flags selects either the increment or decrement mode for the DI and/or SI registers during string operations?

Pentium Pro

Which has 36-bit address bus and therefore can access 64GB of memory

No L2 cache

Which is NOT a version of Pentium Pro?

Cache

Which is examined first when processor need to read data from main memory

Branch prediction logic

Which is included in the IFDU?

Bus Snooping

Which is not Dynamic Execution Technology?

242-pin SECC

Which is not a feature of the Pentium II

R15W

Which is not a word-sized register?

Make instructions to multi-task

Which is not goal of RISC?

L2 cache

Which is/are an improvement(s) of Pentium Pro over Pentium?

RPL > DPL

Which of the following conditions allow access to the segment?

Halt

Which of the following is a special bus cycle

JMP [2], JMP [0123]

Which of the following is an example of Relative program addressing?

0000 0020H

Which of the following is an invalid Pentium Bus Address

a,c,d

Which of the following segment offset combinations points to a common physical memory address? a.) A1B2:000C, b.) A1B0:200C, c.) A1B0:002C, d.) A1B1:001C

Itanium

Which processor is influenced by the EPIC philosophy?