COMP 3500 M6 question bank

Ace your homework & exams now with Quizwiz!

A system has a physical space of size 2 GB (1G = 2^30) and page size = 512 bytes. If paging is used, each entry in the page table will have _______ bits.

Select the best answer. A CPU has a 32 bit address bus and page size = 1024. If paging is used, the page table will have about _______ entries. 2M 512K 1 M 4M None of these answers

A CPU has a 32 bit address bus and page size = 4096 bytes. The CPU generates the address A = 0x2750 8FC3. For this system, the page number is _______ and the page offset is ______ in hexadecimal (Do not forget the "0x" prefix).

0x27508 0xFC3

Fill in the blank. Use the page table below to answer this question. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions by preceding your answer with "0x". Top entry in the page table is for Page 0. Page 3 is stored in Frame ______. 0x1102 0x038A 0x8240 0xA2B3 0x2000 0x00C5 0x054E 0x23F4

0xA2B3

In general, the logical space is larger than the physical space.

True

In terms of memory, the user/programmer sees where the physical space is located inside the logical space where his/her logical space is located inside the physical space a flat logical space starting at address 0 a flat physical space

a flat logical space starting at address 0

In a simple page table, each entry contains at least ______________.

a frame number

A system uses contiguous allocation with equal fixed partitions. As seen on the picture, the operating system can assign fixed partitions B, D, F. When Process 11 arrives, these issues/solutions will be raised or needed. ContiguousAllocationExercise3.png

internal fragmentation

Use the page table below to answer this question. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions by preceding your answer with "0x". Top entry in the page table is for Page 0. Page 6 is stored in Frame ______.

0x054E

Consider a CPU with a 32 bit address bus and a 8192 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x7128. The page offset is _____ . The page number is _____. The frame # is _____. Then the physical address is _____.

0x1128 0x3 0xA2B3 0x14567128

A CPU has a 32 bit address bus and page size = 8192 bytes. The CPU generates the address A = 0x27508103. For this system, the page number is _________ and the page offset is ___________ in hexadecimal (Do not forget the "0x" prefix).

0x13A84 0x103

A CPU has a 32 bit address bus and page size = 512 bytes. The CPU generates the address A = 0x27508103. For this system, the page number is _______ and the page offset is _______ in hexadecimal (Do not forget the "0x" prefix).

0x13A840 0x103

Fill in multiple blanks. Consider a CPU with a 32 bit address bus and a 512 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x54A. The page offset is ______ . The page number is ______ . The frame # is ______ . Then the physical address is ______ . 0x1102 0x038A 0x8240 0xA2B3 0x2000 0x00C5 0x054E 0x23F4

0x14A 0x2 0x8240 0x104814A

Fill in multiple blanks. Consider a CPU with a 32 bit address bus and a 512 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0xD6C. The page offset is ______ . The page number is ______ . The frame # is ______ . Then the physical address is ______ . 0x1102 0x038A 0x8240 0xA2B3 0x2000 0x00C5 0x054E 0x23F4

0x16C 0x6 0x54E 0xA9D6C

Fill in multiple blanks. Consider a CPU with a 32 bit address bus and a 4096 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x2017. The page offset is ______ . The page number is ______ . The frame # is _____ . Then the physical address is ______ . 0x1102 0x038A 0x8240 0xA2B3 0x2000 0x00C5 0x054E 0x23F4

0x17 0x2 0x8240 0x8240017

Fill in multiple blanks. Consider a CPU with a 32 bit address bus and a 1024 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0xDA0. The page offset is ______ . The page number is ______ . The frame # is ______ . Then the physical address is ______ . 0x1102 0x038A 0x8240 0xA2B3 0x2000 0x00C5 0x054E 0x23F4

0x1A0; 0x3; 0xA2B3; 0x28ACDA0

Fill in the blank. Use the page table below to answer this question. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions by preceding your answer with "0x". Top entry in the page table is for Page 0. Page 7 is stored in Frame ______. 0x1102 0x038A 0x8240 0xA2B3 0x2000 0x00C5 0x054E 0x23F4

0x23F4

0x27508 0xFC3

Consider a CPU with a 32 bit address bus and a 1024 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x78E. The page offset is ______ . The page number is ______ . The frame # is ______ . Then the physical address is ______ .

0x38E 0x1 0x38A 0xE2B8E

A CPU has a 32 bit address bus and page size = 2048 bytes. The CPU generates the address A = 0x27508103. For this system, the page number is _______ and the page offset is _______ in hexadecimal (Do not forget the "0x" prefix).

0x4EA10 0x103

Consider a CPU with a 32 bit address bus and a 512 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x85B. The page offset is _____. The page number is _____. The frame # is _____. Then the physical address is _____.

0x5B 0x4 0x2000 0x40005B

Fill in multiple blanks. Consider a CPU with a 32 bit address bus and a 4096 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x6F5. The page offset is 0x6F5 . The page number is 0x0 . The frame # is 0x1102 . Then the physical address is 0x11026F5 .

0x6F5 0x0 0x1102 0x11026F5

Consider a CPU with a 32 bit address bus and a 2048 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x2FC2. The page offset is _____. The page number is _____. The frame # is _____. Then the physical address is _____.

0x7C2 0x5 0xC5 0x62FC2

Consider a CPU with a 32 bit address bus and a 512 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0xA7D. The page offset is _____ . The page number is _____. The frame # is _____. Then the physical address is _____.

0x7D 0x5 0xC5 0x18A7D

0x8240

Fill in multiple blanks. A CPU has a 32 bit address bus and page size = 1024. The CPU generates the address A = 0x27508103. For this system, the page number is ______ and the page offset is ______ in hexadecimal (Do not forget the "0x" prefix).

0x9D420 0x103

Consider a CPU with a 32 bit address bus and a 4096 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x7DE4. The page offset is ______ . The page number is ______ . The frame # is ______ . Then the physical address is ______ .

0xDE4 0x7 0x23F4 0x23F4DE4

Consider a CPU with a 32 bit address bus and a 4096 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x1F06. The page offset is ______. The page number is _____. The frame # is _____. Then the physical address is _____.

0xF06 0x1 0x38A 0x38AF06

Select the best answer. 4 processes are running on a system. There (is) are ______ independent physical space(s). 3 4 None of these answers 2 1

With classical contiguous allocation (no paging), it takes _________ memory access(es) to access an instruction or data.

Fill in multiple blanks. A CPU has a 32 bit address bus and page size = 1024. For this system, the page offset has _______ bits and the page number has ________ bits.

10 22

Fill in multiple blanks. A CPU has a 32 bit address bus and page size = 4096. For this system, the page offset has ______ bits and the page number has _______ bits.

12 20

A CPU has a 32 bit address bus and page size = 8192. For this system, the page offset has _____ bits and the page number has _____ bits.

13 19

Select the best answer. A CPU has a 32 bit address bus and page size = 4096. If paging is used, the page table will have about _______ entries. 128K None of these answers 1 M 512K 256K

A system has a physical space of size 256 MB (1M = 2^20) and page size = 4096 bytes. If paging is used, each entry in the page table will have _______ bytes.

With simple paging, it takes _________ memory access(es) to access an instruction or data.

A system has a physical space of size 1 GB (1G = 2^30) and page size = 1024 bytes. If paging is used, each entry in the page table will have _______ bits.

Select the best answer. A CPU has a 32 bit address bus and page size = 2048. If paging is used, the page table will have about _______ entries. 256K 2M None of these answers 512K 1 M

Select the best answer. A CPU has a 32 bit address bus and page size = 2048. If paging is used, the page table will have about _______ entries. None of these answers 256K 1 M 2M 512K

A memory system is using paging with TLBs. The CPU generated 2400 memory references were performed. Of these memory references 1800 were hits. There were ________ memory accesses to the main memory.

3000

4 processes are running on a system. There (is) are ______ independent logical space(s). 1 3 4 None of these answers 2

Select the best answer. A CPU has a 32 bit address bus and page size = 1024. If paging is used, the page table will have about _______ entries. 1 M 512K 2M None of these answers 4M

This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x2000 and CS = 0x5000. Consider this instruction at address 0600h MOV DH, [1000h] The physical address of the above instruction is ______ and the physical address of the operand [1000h] is ______ .

50600h 21000h

Select the best answer. A CPU has a 32 bit address bus and page size = 8192. If paging is used, the page table will have about _______ entries. None of these answers 256K 512K 1 M 128K

512K

Fill in multiple blanks. (Your answer must be given in hexadecima: do not forget "h" at the end) This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x0400 and CS = 0x5000. Consider the memory access instruction is at address 2000h MOV SI, C120h MOV BX,[SI] The physical address of the memory access instruction is _______ and the physical address of its memory operand is _________.

52000h 10120h

A memory system is using paging with TLBs. The CPU generated 2400 memory references were performed. Of these memory references 1800 were hits. There were ________ memory accesses to the page table in main memory.

600

Check all that apply. Pages can have these sizes: 800 1000 8192 4095 1024

8192 1024

Select the best answer. A system uses contiguous allocation with variable partitions and First-fit policy. As seen on the picture, Process 11 arrives and needs memory. Scanning bottom to up, the operating system will assign to it the slot _________. ContiguousAllocationExercise.png B Process 10's slot None of these answers C A

Select the best answer. A system uses contiguous allocation with variable partitions and Worst-fit policy. As seen on the picture, Process 11 arrives and needs memory. Scanning bottom to up, the operating system will assign to it the slot _________. ContiguousAllocationExercise.png None of these answers C Process 10's slot B A

TLBs are used to ___________________________. None of these answers eliminate internal fragmentation in paging eliminate external fragmentation in paging minimize the memory access time alleviate the space overhead of paging

Minimize the memory access time

A system uses contiguous allocation with equal fixed partitions. As seen on the picture, the operating system can assign fixed partitions B, D, F. When Process 11 arrives, the operating system will certainly assign _______________. ContiguousAllocationExercise4.png Partitions A and B Partition D Partitions B and D Partition B None of these answers

None of these answers

Select the best answer. A system uses contiguous allocation with variable partitions and first-fit policy. As seen on the picture, Process 11 arrives and needs memory. Scanning bottom to up, the operating system will assign to it the slot _________. ContiguousAllocationExercise2.png None of these answers C A Process 2's slot B

None of these answers

Suppose that a system performs address binding at compile time. Check all that applies. Without coordination during compilation, some programs will never execute concurrently on such systems The exact same binary program can execute correctly in different locations in the physical space This system offers great flexibility for the operating system to place programs. A program can be moved around the physical space and still execute correctly Every program can correctly work only in a specific location in the physical space The user/programmer knows in advance (when working on her source) where the program will execute Physical addresses are equal to their associated logical addresses. Every program can correctly work wherever it is loaded

PARTIAL (1.5/2) Every program can correctly work only in a specific location in the physical space The user/programmer knows in advance (when working on her source) where the program will execute (Biaz says this one should not be highlighted)Physical addresses are equal to their associated logical addresses.

Consider a CPU with a 32 bit address bus and a 2048 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x30D3. The page offset is ________. The page number is _____. The frame # is _______. Then the physical address is ________.

PARTIAL - 12/16 0xD3 0x6 0x54E probably 0x2A70D3

Check all that apply about TLBs TLBs store in general the full page table access time to TLBs is faster than access time to main memory TLBs is a kind of cache. TLBs are stored in the main memory Cost per byte is more expensive on TLBs than main memory

TLBs is a kind of cache Cost per byte is more expensive on TLBs than main memory Access time to TLBs is faster than access time to main memory

Check all that apply to logical address translation. The physical address is always different from the logical address Address translation is implemented in software The memory management unit may be inside the CPU The address translation consists always of an addition Different CPU may have different translation schemes

The memory management unit may be inside the CPU Different CPU may have different translation schemes

Consider a CPU with a 32 bit address bus and a 8192 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x8239. The page offset is ______. The page number is ______. The frame # is ______. Then the physical address is ______. .

The page offset is 0x239 The page number is 0x4 The frame # is 0x2000 Then the physical address is 0x4000239.

Select on the dropdown menu whether a policy will in general incur internal or external fragmentation. Policies Internal Fragmentation External Fragmentation Fixed size partitioning ______ ______ Variable size partitioning ______ ______

Yes No No Yes

Select the best answer for each dropdown menu. Select on the dropdown menu whether a policy will in general incur internal or external fragmentation. Policies Internal Fragmentation External Fragmentation Fixed size partitioning Variable size partitioning Paging

Yes, No No, Yes Yes, No

Select the best answer. A system uses contiguous allocation with equal fixed partitions. As seen on the picture, the operating system can assign fixed partitions B, D, F. The operating system will certainly assign ________ to Process 11. ContiguousAllocationExercise3.png Partition C None of these answers Partition A any available partition Partition B

any available partition

The CPU accesses the main memory to fetch busses data addresses instructions

data instructions

On modern systems, address binding is performed at ______________. execution time linking time running time compile time load time

execution time running time

The physical space is infinite.

false

In order to eliminate external fragmentation, the operating system divides the process in equal sized pieces that it can scatter in the physical space. The equal sized pieces (host) in the physical space are called _________.

frames

A systemuses contiguous allocation with variable partitions and first-fit policy. As seen on the picture, Process 11 arrives and needs memory. Scanning bottom to up, the operating system will search for a slot. It seems that these issues/solutions will be raised or needed. ContiguousAllocationExercise2.png

memory compaction external fragmentation

A system uses contiguous allocation with variable partitions and first-fit policy. As seen on the picture, Process 11 arrives and needs memory. Scanning bottom to up, the operating system will search for a slot. The operating system will assign ______ slot. Otherwise, it may consider ______ and move Process ______ . ContiguousAllocationExercise2.png

no memory compaction process 5 right below Process 10

There are five processes running on a system. There are then _____. five inverted page tables and one physical space one inverted page table and five logical spaces one inverted page table and one logical space None of these answers Five inverted page tables and five physical spaces

one inverted page table and five logical spaces

A simple page table is indexed by the ___________.

page numbers

In order to eliminate external fragmentation, the operating system divides the process in equal sized pieces that it can scatter in the physical space (in also equal sized pieces). In order to record and keep track of where the small pieces are located in the physical space, the operating system uses a __________________.

page table

In order to eliminate external fragmentation, the operating system divides the process in equal sized pieces that it can scatter in the physical space. The equal sized pieces in the logical space are called _________.

pages

Select the best answer. A system uses contiguous allocation with equal fixed partitions. As seen on the picture, the operating system can assign fixed partitions B, D, F. When Process 11 arrives, the operating system must _______________. ContiguousAllocationExercise4.png move Process 2 to Partition E move around processes consider memory compaction reject Process 11 for lack of memory None of these answers

reject Process 11 for lack of memory

In order to totally eliminate external fragmentation, _______________________. the OS could perform memory compaction once a day the OS could allow variable partitions the OS could fragment the processes and place them in slots not necessarily contiguous the OS could use fixed size partitions with the option to merge adjacent partitions

the OS could fragment the processes and place them in slots not necessarily contiguous

The CPU can directly access _______________. the hard drive the main memory the secondary storage in general the CPU registers

the main memory the CPU registers

Check all that apply when a miss occurs using TLBs with paging. the memory access time is higher than 2 the memory access time is higher than when TLBs are not used the memory access is still better than simple contiguous placement strategies The memory access time is at least twice the access without paging

the memory access time is higher than 2 the memory access time is higher than when TLBs are not used the memory access time is at least twice the access without paging

Check all that apply when a hit occurs using TLBs with paging. The memory access time is at most half the access without paging the memory access time is higher than 2 the memory access is better than simple contiguous placement strategies The memory access time is at most half the access with paging the memory access time is smaller than when TLBs are not used

the memory access time is smaller than when TLBs are not used

A memory system is using paging with TLBs. The CPU generated 2400 memory references were performed. Of these memory references 1800 were hits. The hit ratio is then ________.

0.75

If there are decimal answers, round up to two decimals. For example, type in "2.67" for "2.66667" and "2.50" for "2.5". If your answer is integer, no need of decimals. A memory system is using paging with TLBs. The CPU generated 5000 memory references were performed. Of these memory references 4250 were hits. We assume that the memory time access to the main memory is 1 (some unit time). The access time to the TLBs is 1/20 (0.05). We want to find the effective (average) access time for the memory references generated above by the CPU. 1) The hit ratio is _______. 2) In total, the memory references that were hits took ____ access time. 3) The number of misses were ______. 4) In total, the memory references that were misses took ______ access time. 5) The average access time for all memory references is _______. 6) Based on the formula for the effective (average) access given in the lecture, the effective (average) access time for all memory references is _______. 7) The difference between the results of Questions 6 and 7 should be _______.

0.85 4462.5 750 1537.5 1.2 1.2 0

If there are decimal answers, round up to two decimals. For example, type in "2.67" for "2.66667" and "2.50" for "2.5". If your answer is integer, no need of decimals. A memory system is using paging with TLBs. The CPU generated 3000 memory references were performed. Of these memory references 2700 were hits. We assume that the memory time access to the main memory is 1 (some unit time). The access time to the TLBs is 1/10 (0.1). We want to find the effective (average) access time for the 3000 memory references. 1) The hit ratio is _______. 2) In total, the memory references that were hits took ____ access time. 3) The number of misses were ______. 4) In total, the memory references that were misses took ______ access time. 5) The average access time for all memory references is _______. 6) Based on the formula for the effective (average) access given in the lecture, the effective (average) access time for all memory references is _______. 7) The difference between the results of Questions 6 and 7 should be _______.

0.90 2970 300 630 1.2 1.2 0

If there are decimal answers, round up to two decimals. For example, type in "2.67" for "2.66667" and "2.50" for "2.5". If your answer is integer, no need of decimals. A memory system is using paging with TLBs. The CPU generated 5000 memory references were performed. Of these memory references 4500 were hits. We assume that the memory time access to the main memory is 1 (some unit time). The access time to the TLBs is 1/20 (0.05). We want to find the effective (average) access time for the memory references generated above by the CPU. 1) The hit ratio is _______. 2) In total, the memory references that were hits took ____ access time. 3) The number of misses were ______. 4) In total, the memory references that were misses took ______ access time. 5) The average access time for all memory references is _______. 6) Based on the formula for the effective (average) access given in the lecture, the effective (average) access time for all memory references is _______. 7) The difference between the results of Questions 6 and 7 should be _______.

0.90 4725 500 1025 1.15 1.15 0

If there are decimal answers, round up to two decimals. For example, type in "2.67" for "2.66667" and "2.50" for "2.5". If your answer is integer, no need of decimals. A memory system is using paging with TLBs. The CPU generated 4000 memory references were performed. Of these memory references 3800 were hits. We assume that the memory time access to the main memory is 1 (some unit time). The access time to the TLBs is 1/20 (0.05). We want to find the effective (average) access time for the memory references generated above by the CPU. 1) The hit ratio is _______. 2) In total, the memory references that were hits took ____ access time. 3) The number of misses were ______. 4) In total, the memory references that were misses took ______ access time. 5) The average access time for all memory references is _______. 6) Based on the formula for the effective (average) access given in the lecture, the effective (average) access time for all memory references is _______. 7) The difference between the results of Questions 6 and 7 should be _______.

0.95 3990 200 410 1.1 1.1 0

This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x0000 and CS = 0x0000. Consider the memory access instruction is at address 0000h MOV SI, 2000h MOV BX,[SI] The physical address of the memory access instruction is ______ and the physical address of its memory operand is ______ .

00000h 02000h

This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x0000 and CS = 0x0000. Consider the memory access instruction is at address 0000h MOV SI, E002h MOV BX,[SI] The physical address of the memory access instruction is ______ and the physical address of its memory operand is ______ .

00000h 0E002h

Fill in multiple blanks. (Your answer must be given in hexadecima: do not forget "h" at the end) This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x0000 and CS = 0x0000. Consider the memory access instruction is at address 0000h MOV SI, 0000h MOV BX,[SI] The physical address of the memory access instruction is __________ and the physical address of its memory operand is __________ .

0000h 0000h

This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x0000 and CS = 0x0000. Consider the memory access instruction is at address 1000h MOV SI, A000h MOV BX,[SI] The physical address of the memory access instruction is ______ and the physical address of its memory operand is ______ .

01000h 0A000h

This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x2000 and CS = 0x0000. Consider this memory access instruction at address 7000h MOV SI, 3000h MOV BX,[SI] The physical address of the memory access instruction is ______ and the physical address of its memory operand is ______ .

07000h 23000h

This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x0000 and CS = 0x0000. Consider the memory access instruction is at address F000h MOV SI, 40A0h MOV BX,[SI] The physical address of the memory access instruction is ______ and the physical address of its memory operand is ______ .

0F000h 040A0h

Fill in the blank. Use the page table below to answer this question. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions by preceding your answer with "0x". Top entry in the page table is for Page 0. Page 5 is stored in Frame ______. 0x1102 0x038A 0x8240 0xA2B3 0x2000 0x00C5 0x054E 0x23F4

0x00C5

Suppose that a system performs address binding at execution time. Check all that applies. After loading, a program can be moved around the physical space and still execute correctly Physical addresses are equal to their associated logical addresses. Without coordination during compilation, some programs will never execute concurrently on such systems This system offers great flexibility for the operating system to place programs After loading, every program can correctly work only in a specific location in the physical space The exact same binary program can execute correctly in different locations in the physical space Every program can correctly work wherever it is loaded The user/programmer knows in advance (when working on her source) where the program will execute

After loading, a program can be moved around the physical space and still execute correctly This system offers great flexibility for the operating system to place programs The exact same binary program can execute correctly in different locations in the physical space Every program can correctly work wherever it is loaded

Check all the features that the user desires in terms of memory from the operating system. Know exactly where his/her program and data are physically stored An infinite memory A sophisticated memory A fast memory An inexpensive memory

An infinite memory A fast memory An inexpensive memory

A system uses contiguous allocation with variable partitions with Best-fit policy. As seen on the picture, Process 11 arrives and needs memory. Scanning bottom to up, the operating system will assign to it the slot _________. B C A Process 10's slot None of these answers

Fill in multiple blanks. (Your answer must be given in hexadecima: do not forget "h" at the end) This exercise is about address translation on an x86 Intel CPU. This CPU translates (using hardware) a logical address LA into a physical address PA as follows: if (LA references data) PA = 10h*DS + LA else // LA references an instruction, i.e. LA is in Register IP: the instruction pointer PA = 10h*CS + IP Suppose DS = 0x0000 and CS = 0xF000. Consider the memory access instruction is at address 2000h MOV SI, A0A0h MOV BX,[SI] The physical address of the memory access instruction is _________ and the physical address of its memory operand is _________ .

F2000h A0A0h

There are five processes running on a system. There are then _____. one page table and one physical space five page tables and no physical spaces None of these answers one page table and one logical space five page tables and five logical spaces

Five page tables and five logical spaces

There are five processes running on a system. There are then _____. five page tables and five physical spaces five page tables and one physical space one page table and one physical space None of these answers one page table and one physical space

Five page tables and one physical space

A driver wants to park along a street with no assigned/marked spots. We assume that he has a huge truck with solid bumper guards. Furthermore, he is drunk and ruthless. Check all that apply. He may experience internal fragmentation He will be using variable partition allocation He may experience external fragmentation He will be using equal size fixed partitions allocation He will use contiguous placement If there is enough available, but scattered space he may use a technique similar to memory compaction.

He will be using variable partition allocation He may experience external fragmentation If there is enough available, but scattered space he may use a technique similar to memory compaction He will use contiguous placement

A driver is trying to park in a downtown parking with walled spots. We assume that the driver has a compact car. Furthermore, he is sober and takes care of his car. Check all that apply. He will be using equal size fixed partitions allocation He will use contiguous placement He may experience external fragmentation He may experience internal fragmentation He will be using variable partition allocation If there is enough available, but scattered space he may use a technique similar to memory compaction.

He will use contiguous placement He will be using equal size fixed partitions allocation He may experience internal fragmentation

Memory compaction is expensive because It must be often used It must use the CPU to select the right processes to move It eventually moves a lot of data from memory to O/I It eventually moves a lot of data from memory to memory

It eventually moves a lot of data from memory to memory It must use the CPU to select the right processes to move It must be often used

Address translation in paging is performed on systems by _____. The objective of this exercise is to write a program to perform address translation for a CPU that has a 32 bit address bus and a 4096 byte page size. We want to use the most efficient code possible (i.e. fast): recall that any instruction related to division is expensive (in time). The variables are named such that they are self explanatory. pageOffset = _____ frameOffset = _____ pageNumber = _____ frameNumber = _____ physicalAddress = _____

PARTIAL - 13.33/16 1=hardware 2=logicalAddress & 0xfff 3=phyicalAddress & 0xfff 4=logicalAddress >> 12 5=pageTable[pageNumber] 6=frameNumber << 12 + pageOffset PARTIAL - 2.67/4 1=hardware 2=logicalAddress & 0xfff 3=phyicalAddress & 0xfff 4=logicalAddress % pageSize 5=pageTable[pageNumber] 6=frameNumber << 12 + pageOffset

Consider a CPU with a 32 bit address bus and a 1024 byte page size. Use the page table below to answer these questions. Each entry of table contains an hexadecimal value (starts with "0x"). Make sure to answer these questions with adding the prefix "0x" and omit leading zeros if any. Top entry in the page table is for Page 0. The objective is to translate the logical address LA =0x27D. The page offset is ______ . The page number is ______ . The frame # is ______ . Then the physical address is ______ .

Partial Credit: 8/16 probably 0x27D 0x0 0x1102 probably 0x440A7D

Suppose that a system performs address binding at load time. Check all that applies. This system offers great flexibility for the operating system to place programs After loading, a program can be moved around the physical space and still execute correctly The exact same binary program can execute correctly in different locations in the physical space Physical addresses are equal to their associated logical addresses. After loading, every program can correctly work only in a specific location in the physical space Every program can correctly work wherever it is loaded The user/programmer knows in advance (when working on her source) where the program will execute Without coordination during compilation, some programs will never execute concurrently on such systems

Physical addresses are equal to their associated logical addresses. After loading, every program can correctly work only in a specific location in the physical space Every program can correctly work wherever it is loaded

See all study sets

COMP 3500 M6 question bank

Related study sets

Psychology Chapter 5

BUSERV exam 2

Accounting

AP World History Chapter 34

Quiz 2

BA 370 EXAM 3 UNGRADED QUIZZES COMBINED

Study Guide for Grains and Legumes

GI prepU

Chapter 24 Mastering quiz bio 2

Astronomy Midterm UCLA

Science earth and space

PF Final

Personal Finance Credit

N122 Quiz 1

Chapter 15 Interpersonal & Organizational Communication

Chapter 23: The Skeletal System

Chapter 11 Wireless Network standards

The Containment Policy of the United States, 1945-1954

Unit 15 - Tax Considerations

US History: Chapter 13