Computer Internal Test 2
The third step in the Fetch-execute cycle is A) fetch instructions (B)fetch operands C) increment LC D) test for interrupts E) execute operands
(B)fetch operands
When an instruction is temporarily unable to continue through the stages of a pipeline it is said to be A) stuck. B) in an overflow. (C)in a stall. D) halted.
(C)in a stall.
Which is NOT part of the Fetch-Execute Cycle? A) Fetch the instruction. B) Increment LC and examine opcode for operands. C) Fetch the operands D) Execute the operation -- leave the result in the ALU (E)Move the instruction back to RAM
(E)Move the instruction back to RAM
For the instruction sequence shown below, how many pipeline stalls will occur? [Note: Another sequence might be substituted.] Instruction K: add register 1 to register 2 and store in register 5. Instruction L: add register 2 to register 3 and store in register 4. A) 0 B) 1 C) 2 D) 3 E) 4
A) 0
General purpose registers are usually numbered from A) 0 through N-1 B) 0 through infinity C) 1 through N D) A through Z E) some large integer to another larger integer.
A) 0 through N-1
A low-level language has which of the following characteristics? A) One-to-one translation. B) Many-to-one translation. C) Hardware independence. D) General purpose. E) None of the above.
A) One-to-one translation.
Which of the following is the slowest way to pass arguments? A) Put the values in memory, in a set place. B) Put the values in general purpose registers. C) Put the values in some special purpose registers. D) Use a window with the general purpose registers. E) Put the values in cache.
A) Put the values in memory, in a set place.
What mechanism is used to perform out-of-order instructions? A) Scoreboard B) Accumulator C) Cache D) All of the abovevon E) None of (A), (B), or (C).
A) Scoreboard
Something that records the status of an instruction's result is known as A) condition code B) microcode C) stack architecture D) all of the above E) none of (A), (B), or (C).
A) condition code
Minimal circuit design requires A) fewer instructions. B) larger instruction sets. C) instruction sets that provide more convenience for the programmer. D) instruction sets that allow programmers to write fewer instructions to carry out desired operations. E) all of the above.
A) fewer instructions.
On a computer that follows the Von Neumann architecture, the time spent performing memory accesses can limit the ___ A) overall performance B) memory extraction C) operand functionality D) usability of registers E) none of the above.
A) overall performance
Using reverse Polish notation, what is the answer to 1 2 3 + - A) 0 B) -4 C) 6 D) 4 E) 3
B) -4 --> 1-(2+3)
A directive does NOT A) Relate to keywords .word and .long. B) Correspond to an instruction. - pg 129 C) Control translation. D) Specify that storage locations should be reserved to hold variables. E) Allow a programmer to specify an initial value.
B) Correspond to an instruction.
An assembler makes how many conceptual passes? A) It does everything in 1 pass. B) It takes two -- one to assign locations to each statement and a second to generate code. C) It takes up to five, depending on the intensity of code. D) It takes one half pass. E) None of the above.
B) It takes two -- one to assign locations to each statement and a second to generate code.
What happens to operands that are not needed in a fixed-length instruction architecture? A) They are replaced by zeroes. B) They are ignored. C) They are moved to the registers, but not used in the calculations. D) They are taken as alternates if fetching the primary operand encounters a problem. E) They are not allowed.
B) They are ignored.
The basic issue of the Von Neumann bottleneck is that A) disk access is very slow. B) memory access can become a bottleneck. C) operands in registers may not be available. D) immediate operands must be fetched. E) none of the above.
B) memory access can become a bottleneck.
The LC is incremented during what stage of pipeline operation? A) 1 B) 2 C) 3 D) 4 E) 5
B)2
An operand that is not yet available from a previous instruction will cause a stall at stage ___ of a pipeline. A) 1 B) 2 C) 3 D) 4 E) 5
C) 3
Which of the following is NOT an operand that might specify a source? A) A signed constant. B) An unsigned constant. C) A value at a specific disk address. D) The contents of a register. E) The value in a specific memory location.
C) A value at a specific disk address.
Which of the following takes a register value and interprets it as a memory address? A) Direct register reference. B) Direct memory reference. C) Indirect through register reference. D) Indirect through memory reference. E) None of the above.
C) Indirect through register reference.
What does the branching acronym bneq mean: A) branch only if equal to B) branch if equal to C) branch if not equal to D) branch at the next equal to statement E) none of the above.
C) branch if not equal to
The directive used for 16-bit items is A) .16 B) .long C) .short D) .word E) .book
D) .word
An instruction fed to a stack computer might read: A) Add 1, 2, 3 B) Add 1, 2 C) Add stack 1, stack 2 D) Add - stack computers have 0-addresses E) None of the above.
D) Add - stack computers have 0-addresses
The set of operations a processor provides represents a tradeoff. Which of the following are included in the tradeoff considerations? A) The cost of the hardware. B) The Convenience for a programmer. C) Engineering considerations such as power consumption. D) All of the above. E) None of (A), (B), or (C).
D) All of the above.
Which of the following is NOT part of the CPU? A) Graphics engine. B) ALU. C) Query engine. D) BIOS. E) All of the above ARE parts of the CPU.
D) BIOS.
Which of the following is the least expensive operand addressing mode? A) Direct memory reference. B) Indirect through a register reference. C) Indirect memory reference. D) Immediate value. E) Direct disk reference.
D) Immediate value.
Which of the following is NOT a cause of pipeline stalls? A) Access external storage. B) Call a subroutine. C) Branch to a new location. D) Retrieve information from a register. E) Invoke a coprocessor.
D) Retrieve information from a register.
The instruction br +8 is an example of A) an absolute branch. B) a register window. C) a function call. D) a relative branch instruction. E) none of the above.
D) a relative branch instruction.
CISC processors contain A) many instructions that take only one clock cycle. B) few instructions, but each may take several clock cycles to execute. C) the same instruction set as RISC processors, but they are more stable. D) more instructions than a RISC processor, some of which take more than one clock cycle to execute. E) none of the above.
D) more instructions than a RISC processor, some of which take more than one clock cycle to execute.
Which of the following is a type of operation? A) Integer arithmetic B) Boolean instructions C) Data access & transfer instructions D) Floating-point instructions E) All of the above.
E) All of the above.
Microcode is A) at a level below the machine language. B) implemented with digital logic. C) a way to provide backward compatibility. D) used to implement the fetch-execute cycle. E) all of the above.
E) all of the above.
Modes of operation can provide A) different subsets of instructions that are valid. B) different sizes of data items. C) access to different regions of memory. D) access to different functional units. E) any of the above.
E) any of the above.
A 1-address architecture is also known as a stack machine.
False
A programmable processor is one that accesses programs from a hard disk.
False
A relative branch specifies the address of the next instruction to execute.
False
A stack machine is also called a one-address code machine.
False
A stack machine requires two accumulators.
False
A two-pass assembler gives the programmer an opportunity to correct errors during the second pass.
False
All pipelines use the 5-stage model we've discussed.
False
An assembler takes binary code and translates it into assembly language for the processor to execute.
False
An operation on a stack computer uses two operands and leaves the result on the stack.
False
Beginning a statement with a "#" in assembly language usually refers to a subroutine.
False
CISC processes individual instructions faster than RISC does.
False
Condition codes are used to determine which register a value is to be stored in.
False
Every computer architecture uses condition codes.
False
General-purpose registers were the forerunners of the accumulator.
False
If we want to use a subroutine, all we need to do is to be able to jump to the address where the subroutine is located.
False
Immediate operands are stored in the Immediate register.
False
In a MIPS processor, register 0 cannot be used, except in Add or Sub instructions
False
It is always more efficient to write code in assembly language than in a high-level language.
False
It is easier to make circuit boards than to implement microcode instructions.
False
Only privileged instructions set the condition code.
False
Pipelined machines operate best with CISC.
False
RISC is likely to include an instruction to manipulate graphics in memory.
False
The "local storage" in a conventional processor (e.g., Fig. 4.3) is in known locations in RAM.
False
The identification of operands is stored in registers or memory.
False
To use a macro facility, a programmer adds 3 types of items to the source program.
False
Two-address machines use an accumulator to hold results.
False
Two-pass assembly is optional and not recommended.
False
We use the set condition code instruction to establish an initial value for the condition code.
False
When a jump instruction is executed in a pipeline, the CPU must first finish executing all instructions in the pipeline before jumping to the specified instruction.
False
When the CPU is in NON-privileged mode, the OS blocks instructions that perform I/O from being executed.
False
With a 0-address architecture, we must assume that the result is placed in register 1.
False
With an assembler, changing branch labels can be tedious and prone to errors
False
jsr and ret are jump-type instructions that can be used interchangeably.
False
A computer whose architecture uses three operands per instruction must have an accumulator as well.
False (one operand instruction sets)
RISC stands for redux instruction computer set
False (reduced instruction set computing)
A CISC processor includes a minimum instruction set.
False (would be RISC)
A "forward reference" means that the label referenced in a branch is defined later in the program.
True
A CISC(Complex Instruction Set Computing) processor usually includes many instructions and each instruction often performs a complex computation
True
A computer with zero operands is known as a stack architecture.
True
A jmp instruction is also known as an absolute branch.
True
A relative branch instruction does not specify an exact memory address.
True
A stack machine is also called a zero-address code machine.
True
A zero-address architecture uses a stack.
True
All instruction operands are represented by sequences of binary bits in the actual instruction in machine language.
True
An assembly language provides a syntactic form for each possible operand type that the processor supports.
True
Architects use the term method or procedure or subroutine to refer to a piece of code that can be invoked.
True
Conventional computers that store both programs and data in memory are known as Von Neumann computers.
True
In a MIPS processor, register 0 can be used to store values of computation.
True
In computers with fixed-size instructions, we sometimes have operands that are not needed and are ignored by the circuitry.
True
In stage 2 of the execution pipeline, we examine the opcode.
True
Instructions for our paper assembler consist of operations and operands.
True
Opcodes are stored inside the instruction.
True
Pipelined machines operate best with RISC.
True
Pipelining means that several machine instructions are simultaneously in different stages of being executed.
True
Processors are used in all of the following roles: coprocessors, microprocessors, microcontrollers, embedded system processors, and general-purpose processors.
True
Some assembly languages allow register names to be defined by the programmer.
True
The Sub instruction sets the CC. [May give a different instruction.]
True
The ability to carry out Boolean operations is part of the ALU.
True
The assembler translates each instruction's operation into a unique sequence of binary bits.
True
The first step in the Fetch-Execute cycle is to Fetch the next instruction.
True
The identification of operands is stored inside the instruction.
True
The instruction sequence: Add 1, 5, 8 Add 8, 7, 6 would cause a pipeline stall.
True
The pipeline concept allows us to speed up overall execution of programs.
True
The pipeline is transparent to programmers.
True
We say that an instruction set is orthogonal if each instruction performs a unique task.
True
With a 1-address architecture, you must assume the existence of an accumulator.
True
With a our pipeline, every instruction uses 5 clock cycles to completely execute.
True
With two-address code, we must establish a convention as to where the result go.
True