Computer Organization-Comp2340 Tutorials
.What are the different types of fields that are part of an instruction? Explain.
Operation codes field it specifies the operation to be performed for the instruction. Address field it designates the various addresses such as registers and memory address. Mode field it specifies how effective address is derives or how an operand is to perform
What are two senses in which the term "random - access memory " is used ?
(1) A memory in which individual words of memory are directly access through wired-in addressing logic. (2) Semiconductor main memory in which it is possible both to read the data from the memory and to write new data into the memory easily and rapidly
What are the difference among sequential access, direct address and random access?
- SEQUENTIAL ACCESS Memory is organized into units of data called records.Access must be made in specific linear sequence -DIRECT ACCESS Individual blocks or records have a unique address based on physical location. Access is accomplished by direct access to reach general vicinity plus sequential searching , counting, or waiting to reach the final location. -RANDOM ACCESS Each addressable location in memory has a unique physically wired-in addressing mechanism. The time to access a given location is independent of the sequence of prior access and is constant.
List three broad classifications of external, or peripheral, devices.
-Human Readable suitable for communication with the computer user - Machine Readable suitable for communicating with equipment - Communication Suitable for communicating with remote devices
What are the key properties of semi conductor memory ?
-They exhibit two stable ( or semi-stable) states, which can be used t represent binary 1 and 0 -They are capable of being written into (at least once) to set the state -They are capable of being read to sense the state
What are the main facilities that must be provided in a system designed to support the integration of multimedia into a multimedia presentation?
1.Digital Representation of Media -(Many formats for many media) 2.Capture: Digitisation of Media -(special Hardware/Software) 3.Creation and editing - (assemble media and alter it) 4.Storage Requirements -(significant for multimedia) 5.Compression -( related to above and below, i.e. can save on storage but can hinder retrieval) 6.Structuring and retrieval methods of media -( simple to advanced Database Storage) 7.Display or Playback methods - (effect of retrieval must view data) 8.Media Synchronization -( display multimedia as it is intended)
Suppose you have a 4-way set associative cache which has in total 4096 bytes of cache memory and each cache line is 128 bytes. How many sets are there is this cache? If memory is byte addressable and addresses are 16 bits then how many bytes are used for the tag?
4 way set associative Total cache memory =4096 bytes Block size(cache line) =128 byte Number of cache line= 4096/128 =32 lines Number of sets in cache=32/4 =8 sets **rest of answer in tutorial 7
Explain why one type of RAM is considered to be analog and the other is digital
A DRAM cell is essentially an analog device using a capacitor; the capacitor can store any charge value within a range; a threshold value determines whether the charge is interpreted as 1 or 0. A SRAM cell is a digital device, in which binary values are stored using traditional flip-flop logic gate configurations.
An encoded microinstruction format is to be used. Show how a 9-bit micro-operation field can be divided into subfields to specify 46 different actions.
A field of 5 bits yield 2^5 - 1 = 31 different combination of control signals. A field of 4 bits yield 2^4-1= 15 different combination of control signals. so... 31+15=46
What is the difference between a hardwired implementation and a microprogrammed implementation of a control unit?
A hardwire control unit is a combinatorial circuit, in which input logic signals are transformed into a set of output logic signals that function as the control signal. In a micro control unit the logic is specified by a micro program. A micro program consists of a sequence of instructions in a micro programming language. These are simple instructions that specify micro instructions.
What are registers?
A register is a group of binary cells of n-cells that can store any discrete quantity of information that contains n-bits. The state of a register is a n-tuple of 1s and 0s with each bit designating the state of one cell in the register.
What are some of the key benefits of clustering?
AS.IS.HA.SP Absolute scalability: It is possible to create large clusters that far surpass the power of even the largest standalone machines. Incremental scalability: A cluster is configured in such a way that it is possible to add new systems to the cluster in small increments. Thus, a user can start out with a modest system and expand it as needs grow, without having to go through a major upgrade in which an existing small system is replaced with a larger system. High availability: Because each node in a cluster is a standalone computer, the failure of one node does not mean loss of service. Superior price/performance: By using commodity building blocks, it is possible to put together a cluster with equal or greater computing power than a single large machine, at much lower cost.
What is the general relationship among access time, memory cost and capacity?
As access time becomes faster, the cost per bit increases. As memory size increases the cost per bit is smaller. Also, with greater capacity, the access time becomes slower.
Define binary logic?
Binary Logic consists of binary variables and logical operations. The variables are designated by the alphabet such as ABC XYZ etc. with each variable having only two distinct values 1 and 0. There are three basic operations i.e. AND (x), OR (+) and NOT (~).
What are the major functions of an I/O module?
CT.PC.DC.DB.ED CT- Control & timing PC- Process Communication DC-Data Communication DB-Data Bufferring ED-Error Detection
DRAM - DYNAMIC RANDOM ACCESS MEMORY
Dynamic Random Access Memory is a type of memory that is typically used for data or program code that a computer processor needs to function. DRAM is a common type Random Access Memory used in personal computers(PCs), workstations and servers. Random Access allows the PC Processor to access any part of the memory directly rather than having to proceed sequentially from a starting place. RAM is located close to a computer's processor and enables faster access to data than storage media such as hard disk drives and solid state drives.
EEPROM (Electronically Erasable Programmable Read-Only Memory )
EEPROM is a special type of PROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM retains its contents even when the power is turned off. Also; like other types of ROM, EEPROM is not as fast as RAM.EEPROM is similar to flash memory (sometimes called flash EEPROM). The principal difference is that EEPROM requires data to be written or erased by one byte at a time whereas flash memory allows data to be written or erased in blocks.This makes flash memory faster.
EPROM (Erasable Programmable Read-Only Memory)
EPROM is read and written electrically; before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultra-violent light through a window that is designed into the memory chip.
. Explain the steps in an instruction cycle.
FI.DI.F.E.R - Fetch Instruction- the cpu fetches the instruction from memory. The PC gets loaded with the address of the instruction. -Decodes the Instruction In case the instruction has an indirect address, the effective address is read from the memory -Fetch the operand from the memory -Execution -once the instruction gets decoded the processor executes the instruction. -Result -store the result in the appropriate place
Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. What is the maximum memory address space that the processor can access directly if it is connected to a "16-bit memory"?
Hypothetical micro processor generates 16 bit address, PC and address registers are 16 bits wide and 16 bit data bus. That is 16 bit memory. The maximum memory address space that the processor can access directly if it is connected to "16 bit memory" is 2^16 = 65536 approximately 64 kb because the address length consist of 16 bits.
What is the difference between horizontal and vertical microinstructions?
In a horizontal micro instruction every bit in the control field attaches to a control line.In a vertical micro instruction a code is used for each action to be performed and the decoder translates this code into individual control signals
Give several reasons for the choice by designers to move to a multicore organization rather than increase parallelism within a single processor.
In the case of pipelining, simple 3-stage pipelines were replaced by pipelines with 5 stages, and then many more stages, with some implementations having over a dozen stages. There is a practical limit to how far this trend can be taken, because with more stages, there is the need for more logic, more interconnections, and more control signals. With superscalar organization, performance increases can be achieved by increasing the number of parallel pipelines. Again, there are diminishing returns as the number of pipelines increases. More logic is required to manage hazards and to stage instruction resources. Eventually, a single thread of execution reaches the point where hazards and resource dependencies prevent the full use of the multiple pipelines available. This same point of diminishing returns is reached with SMT, as the complexity of managing multiple threads over a set of pipelines limits the number of threads and number of pipelines that can be effectively utilized.
Why are transfers of control instructions needed?
In the practical use of computers it is essential to be able to execute each instruction more than once, and many 1000 times. It may require 1000 or million instruction to implement an application. This would be unthinkable if each instruction had to be written if a table or list of items is to be processed a program loop is needed. 1 sequence of instruction is executed to process all the data. Virtually all programs involve some decision making, we would like the computer to do one thing if one condition holds, and another thing if another condition holds, To compose correctly a large or midsize computer program is an exceedingly difficult task. It helps if there are mechanism for breaking the task up into smaller pieces that can be worked on one at a time.
What is the distinction between instruction-level parallelism and machine parallelism?
Instruction-level parallelism (ILP) of a program is a measure of the average number of instructions in a program that, in theory, a processor might be able to execute at the same time. • Mostly determined by the number of true (data) dependencies and procedural (control) dependencies in relation to the number of other instructions • ILP is traditionally "extracting parallelism from a single instruction stream working on a single stream of data" Machine parallelism of a processor—a measure of the ability of the processor to take advantage of the ILP of the program • Determined by the number of instructions that can be fetched and executed at the same time • A perfect machine with infinite machine parallelism can achieve the ILP of a program
What is MIDI? How is a basic MIDI message structured?
MIDI is a protocol that enables computer, synthesizers, keyboards, and other musical or even multimedia devices to communicate with each other. MIDI Message includes a status byte and up to 2 data bytes. A status byte is the most significant bit and is set to 1. The four low order bits identifies which channel it belongs to.
Assuming the first instruction is at address 0, what is the address of each instruction, and what will be the contents of the PC register after each instruction is obeyed?
Memory is bytes addressable the ARM address is 32 bits long therefore an ARM Instruction is 32 bits long ARM addresses are in bytes units. 4-cond 4-1010 24-effect = 32 bits which specifies the condition for which the instruction will be executed.
List some examples of applications that benefit directly from the ability to scale throughput with the number of cores
Multi-Threaded Native Applications: Multi-threaded applications are characterized by having a small number of highly threaded processes. Examples of threaded applications include Lotus Domino or Siebel CRM (Customer Relationship Manager). Multi-Process Applications: Multi-process applications are characterized by the presence of many single-threaded processes. Examples of multi-process applications include the Oracle database, SAP, and PeopleSoft. Java Applications: Java applications embrace threading in a fundamental way. Not only does the Java language greatly facilitate multithreaded applications, but the Java Virtual Machine is a multi-threaded process that provides scheduling and memory management for Java applications. Java applications that can benefit directly from multicore resources include application servers such as Sun's Java Application Server, BEA's Weblogic, IBM's Websphere, and the open-source Tomcat application server. All applications that use a Java 2 Platform, Enterprise Edition (J2EE platform) application server can immediately benefit from multicore technology. Multi-Instance Applications: Even if an individual application does not scale to take advantage of a large number of threads, it is still possible to gain from multicore architecture by running multiple instances of the application in parallel. If multiple application instances require some degree of isolation, virtualization technology (for the hardware of the operating system) can be used to provide each of them with its own separate and secure environment.
What is meant by the terms Multimedia and Hypermedia? Distinguish between these two concepts.
Multimedia- An application that uses a collection of multiple media sources. Example text,graphics,images,sound or audio.Hypermedia is an application which uses associated relationships among information contained within multiple media data for the purpose of facilitating access to, manipulation of the information encapsulated by the data.
When a device interrupt occurs, how does the processor determine which device issued the interrupt?
Multiple Interrupt Lines : Provides multiple interrupt lines between the processor & I/O nodes. Each line has multiple I/O modules attached. This has the disadvantage of limiting the number of devices. Software Polling : The CPU repeatedly checks the status register of a device to determine whether the device needs service. The disadvantage is that this is slow. Daisy Chain (Hardware Polling, Vectored) : When a processor senses an interrupt it sends an Interrupt Acknowledge down a chain. The signal propagates through a series of I/O modules until it gets to a requesting module. The requesting module typically responds by placing its vector on the data bus, which is read by the processor, and used to generate the address of the interrupt-service routine. If device 1 did not request the servicing, it will pass the interrupt acknowledge signal on to the next device in the chain. Device 2 follows the same procedure, and so on. The CPU uses vectored interrupts which are processing techniques in which the interrupting device directs the processor to the appropriate interrupt service routine.. This avoids the need to execute a general interrupt service. Bus Arbitration (Vectored) -An I/O module must gain control of the bus before it can raise an interrupt. When the processor detects the interrupt, it responds on the interrupt acknowledge line. The requesting module places its vector on the data lines.
List and briefly explain five important instruction set design issues
OR.DT.IF.R.A 1. OPERATIONS REPERTOIRE - how many and which operations to provide, and how complex should operations be. 2.DATA TYPES- various types of data on which operations are performed. 3.INSTRUCTION FORMAT- Instruction length (in bits) numbers of addresses,sizes of various fields 4.REGISTERS- Number of CPU Registers that can be referenced by instructions and their uses. 5.ADDRESSING- The mode or modes by which an opperand is specified.
Consider an L1 cache with an access time of 1 ns and a hit ratio of H 0.95. Suppose that we can change the cache design (size of cache, cache organization) such that we increase H to 0.97 but increase access time to 1.5 ns. What conditions must be met for this change to result in improved performance?
Old System (TS1) = 1ns with H = 0.95 (95%) [cache access time ] New System (TS2) = 1.5ns with H =0.97 (97%) [cache access time ] TS1= 1ns + (1-H) T2 = 1+0.05 T2 TS2=1.5ns + (1-H)T2 =1.5 +0.03 TS2 TS1> =T2 1+0.05 T2 >= 1.5 +0.03T2 For the change to improve performance the average access time of the system while using the larger cache must be smaller than the average access time of the system while using the smaller original cache. For T2 (main memory access time) greater than 25 ns, the change will improve performance. This assumes a two-level memory system. Cost should also be considered.
What are some of the potential advantages of an SMP compared with a uniprocessor?
P.A.IG.S Performance: If the work to be done by a computer can be organized so that some portions of the work can be done in parallel, then a system with multiple processors will yield greater performance than one with a single processor of the same type. Availability: In a symmetric multiprocessor, because all processors can perform the same functions, the failure of a single processor does not halt the machine. Instead, the system can continue to function at reduced performance. Incremental growth: A user can enhance the performance of a system by adding an additional processor. Scaling: Vendors can offer a range of products with different price and performance characteristics based on the number of processors configured in the system.
Summarize the differences among simple instruction pipelining, superscalar, and simultaneous Multithreading.
Pipelining: Individual instructions are executed through a pipeline of stages so that while one instruction is executing in one stage of the pipeline, another instruction is executing in another stage of the pipeline. Superscalar: Multiple pipelines are constructed by replicating execution resources. This enables parallel execution of instructions in parallel pipelines, so long as hazards are avoided. Simultaneous multithreading (SMT): Register banks are replicated so that multiple threads can share the use of pipeline resources.
What are the contents of the registers (R0, R1, R2) and variables (anne, tom, fred) after each of the following instructions is obeyed: LDR R0, anne STR R0, fred LDR R1, tom ADD R2, R0, R1 STR R2, anne SVC 2 The variables start with these values: anne is 23 tom is 45 fred is 10
R0 R1 R2 Anne Tom Fred LDR R0,Anne 23 23 45 10 STR R0,Fred 23 23 45 23 LDR R1,Tom 23 45 23 45 23 ADD R2,R0,R1 23 45 68 23 45 23 STR R2,aAnne 23 45 68 68 45 23 SVC 2 23 45 68 68 45 23
List and briefly define three types of Computer System Organization
SISD.SIMD.MIMD Single Instruction Single Data (SISD)- A single processor executes a single instruction stream to operate on data stored in a single memory. Single instruction, multiple data (SIMD) stream: A single machine instruction controls the simultaneous execution of a number of processing elements on a lockstep basis. Each processing element has an associated data memory, so that each instruction is executed on a different set of data by the different processors. Multiple instruction, multiple data (MIMD) stream: A set of processors simultaneously execute different instruction sequences on different data sets.
(SRAM ) Static Random Access Memory
Static Random Access Memory is random access memory that retains data bits in its memory as long as power is being supplied. Unlike dynamic random access memory , which stores bits in a cells consisting of a capacitor and a transistor, SRAM does not have to be periodically refreshed. SRAM provides faster access to data and it is more expensive than DRAM. SRAM is used for a computer's cache memory and as part of the random access memory digital to analog converter on a video card.
Your ALU can add its two input registers, and it can logically complement the bits of either input register, but it cannot subtract. Numbers are to be stored in two's complement representation. List the micro-operations your control unit must perform to cause a subtraction.
T1: MAR <- IR(address) T2: MBR <- Memory T3: MBR <- Complement (MBR) T4: MBR <- Increment (MBR) T5: MBR <- R1 + MBR
When a DMA module takes control of a bus, and while it retains control of the bus, what does the processor do?
The CPU pauses for each bus cycle taken by the DMA module. Bus Cycle - This is the time required to make a single read/write transaction between the CPU & external memory.
A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.
The cache is divided into 6 sets of 4 lines each.Therefore, 4 bits are needed to identify the set number. Main Memory consists of 4k=212 blocks.Therefore, the set plus tag lengths must be 12 bits and therefore the tag length is 8 bits.Each block contains 128 words.Therefore, 7 bits are needed to specify the word offset. TAG SET WORD Main Memory Address 8 4 7
What are the similarities and the differences between the "3-address" and the "Load-Store" instruction styles?
The similarities are that both are arithmetic instructions and operations. Also, they have 2 inputs operands and has a result operand. The differences are the 3- address operands result in memory locations, while the load store operands result in registers. Instructions move between registers and RAM.
How are data written onto a magnetic disk?
The write- mechanism is based on the fact that electricity flowing through a coil produces a magnetic field. The pulses are sent to the write head, and magnetic patterns are recorded on the surface below with different patterns for negative and positive currents.An electric current in the wire induces a magnetic field across the gap.Which in turn magnetize a small area of the recorded medium.Reversing the direction of the current reverses the direction of the recorded medium.
A two-way set-associative cache has lines of 16 bytes and a total size of 8 kbytes. The 64-Mbyte main memory is byte addressable. Show the format of main memory addresses.
There are a total of 8 kbytes/16 bytes=512 lines in the cache. Thus the cache consists of 256 sets of 2 lines each. Therefore 8 bits are needed to identify the set number.fOR THE 64-MbYTE main memory, a 26 bit address is needed.Mian memory consists of 64 mbytes /16 bytes= 2^22 blocks.Therefore, the set plus tag length must be 22 bits.So the tag is 14 bits and word field is 4 bits TAG SET WORD Main MemoryAddress 14 8 4
Define the terms track, cylinder, and sector
Track- On a magnetic disc data is organized on the platter in a concentric set of rings called Tracks Data are transferred to and from the disc in sectors; for a disc with multiple platters, the set of all tracks in the same relative position on the platter is referred to as a cylinder.
What is the difference between an arithmetic shift and a logical shift?
With a logic shift, the bits of a word are shifted left or right on one end and the bit shifted out is lost, on the other end, a zero is shifted in. The arithmetic shift operation treats the data as a signed integer and does not shift the signed bit. On a right arithmetic shift, the signed bit is replicated into the bit position to its right. On a left arithmetic shift, a logical left shift is performed on all bits but the signed bit which is retained.
Given the following memory values and a one-address machine with an accumulator: Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word 50 contains 70 What values do the following instructions load into the accumulator? a. Load IMMEDIATE 20 b. Load DIRECT 20 c. Load INDIRECT 20 d. Load IMMEDIATE 30 e. Load DIRECT 30 f. Load INDIRECT 30
a. Load Immediate 20 ->Return 20 b.Load Direct 20 ->Return 40 c.Load Indirect 20 ->Return 20-->40--->60 d.Load Immediate 30 --->Return 30 e.Load Direct 30 --->Return 60 f.Load Indirect 30 ---> Return 30 -> 60-->90
Assume that propagation delay along the bus and through the ALU are 20 and 100ns , respectively. The time required for a register to copy data from the bus is 10 ns. What is the time that must be allowed for : a . transferring data one register to another ? b. incrementing the program counter ?
a.Time required = propagation time + copy time = 20 +10 = 30 nanoseconds b. 1. z<-- PC + 1 =20 +100 +10 =130 ns 2. PC <---Z = 20 +10 =30 nanoseconds Total Time Required = 130 +30 = 160 nano seconds
Define logic gates?
are electronic circuits that operate on one or more input signals to produce an output signals. Electrical signals is such that as voltages or currents exist through - out a digital system in either of the 2 recognizable values.Voltage operated circuits response to two separate voltage levels that represents a binary variable = to logic 1 or logic 0
FLASH MEMORY
is intermediate between EPROM and EEPROM in both cost and functionality. Like EEPROM, flash memory uses an electrical erasing technology. An entire flash memory can be erased in one or few secs, which is much faster than EPROM. In addition, it is possible to erase just blocks of memory rather than an entire chip. However, flash memory does not provide byte-level erasure. Like EPROM,flash memory uses only one transistor per bit, and so achieves the high density (compared with EEPROM ) OF EPROM
