CS 271 - Second Half
Macros
For _________, the entire code is substituted for each call.
ESI
What is the implied index for the LODSB instruction?
EDI
What is the implied index for the STOSB instruction?
10 bytes
What is the size of the FPU stack registers?
LOCAL directive
What mechanism allows a macro with labels to be used multiple times in a program?
The preprocessor
What mechanism is responsible for implementing inline expansion?
False - While the setup and takedown of the activation record is handled by the LOCAL directive, the return statement is not. The programmer must still write the return statement and account for any passed parameters.
(True/False) If a procedure uses the LOCAL directive, the procedure doesn't need a RET statement.
FILD
Which instruction is used to convert an integer value to float and push it onto the FPU stack?
FINIT
Which instruction is used to initialize the FPU?
Branching Decision structures repetition structures recursion
Which of the following portions of a program can complicate the instruction-caching process? (Check all that apply)
CMPSB
Which of the following string primitives will compare the BYTEs stored in the memory locations pointed to by EDI and ESI?
STOSB
Which of the following string primitives will copy a BYTE from the AL register to the memory location pointed to by EDI?
LODSB
Which of the following string primitives will copy a BYTE from the memory location pointed to by ESI to the AL register?
MOVSB
Which of the following string primitives will copy a BYTE from the memory location pointed to by ESI to the memory location pointed to by EDI?
Procedures
_________ are translated only once, and can be called many times.
Procedures
_________ have a calling mechanism involving the EIP.
Procedures
_________ have a return mechanism involving the system stack.
False - CISC ISA's have way more instructions
(True/False) RISC architectures tend to have more instructions than CISC.
1. Passed Parameters 2. Procedure Return Address 3. Old EBP Value 4. Local Variables 5. Saved Registers
Please place the following components of the stack frame in the order in which they should be pushed (or room made for them) on the stack.
0
A 0-address FPU instruction will have how many operands?
Contiguous
Arrays elements are stored in ____________ memory.
False
As the number of parallel processors goes to infinity, the runtime of any algorithm will approach 0.
False
Assuming that all processor clock speeds are identical, executing a given software algorithm on a multicore processor is always faster than executing the same algorithm on a single-core processor.
legacy
Backwards compatibility is where new devises continue to support ____________ operations
EAX
For string primitives, which register is the 32-bit accumulator?
5th Element
Given list, an array of WORDs, what element is addressed by list[8]?
FILD will convert an integer value to float before pushing it on the FPU stack. FLD assumes the provided value is already a float.
How is the FILD instruction different than FLD ?
FST will copy the value in ST(0) into a memory location (or stack register), while FSTP will do that, and also remove the copied value from the FPU stack.
How is the FSTP instruction different than FST ?
You attempt to access whatever data bytes are stored there.
If you reference a point beyond the end of an array in MASM (for example, the address of the what would be the 105th element of a 100-element array), what happens?
Multicomputer Parallelism
In Multicomputer Parallelism , each processor has its own individual (distributed) memory and communicate and coordinate through an interconnection network.
Multiprocessor Parallelism
In Multiprocessor Parallelism , all processors access the same (shared) memory and communicate and coordinate through an interconnection network.
On the runtime stack, immediately above the old EBP value
In a procedure using the LOCAL directive, where are the local variables created?
True
In general, RISC instructions execute faster then CISC instructions.
- CISC is simpler to code due to more robust instructions. - RISC generally requires more RAM because the programs themselves are longer in memory (more instructions are required to complete the same task). - CISC having a larger Instruction Set means there's less "reinventing the wheel" for many operations. - CISC also offers backwards compatibility to the vast majority of computers in operation in the world today.
In what ways might CISC be 'better than' RISC? You may need to explore outside resources to answer this question.
A macro is better - The code in the loop is only expanded once, but is executed many times (you will only have one macro expansion but a procedure will occur 1000 times)
Inside a loop which executes 1000 times, is it better to use a macro or a procedure? Why?
None
List some FPU instructions which accept immediate operands.
1. Prioritize single-cycle instruction execution. 2. Instructions executed directly by hardware (no micro-instructions). 3. Cache Instructions to reduce instruction-fetch bottleneck. 4. LOAD/STORE are the only memory access instructions, others are register-register. 5. Simplify Instructions, and use few addressing modes.
List three primary RISC design principles:
RISC - Many embedded devices use a RISC architecture because the design principles generally allow for faster programs.
Most cellphones are built on (RISC? or CISC?) architectures? Why?
True
Multiprocessor Parallelism usually has lower coordination overhead than Multicomputer Parallelism.
False
One of the major limitations of CISC is that its data buses can never be wider than they are now.
True
One of the primary design principles of RISC is to avoid micro-programs and have instructions be directly executed.
True
RISC architectures generally have fewer, simpler instructions that run faster than CISC instruction.
Accessing memory through an address stored in a register.
Register Indirect addressing is defined as follows:
STOSB - 1 byte STOSW - 2 bytes (w refers to word)
STOSW will write how many bytes to memory?
False
Software parallelism is currently much more developed than hardware parallelism.
False
The IA-32 FPU FLD instruction can only load in REAL10 floats, not REAL4 or REAL8.
False
The IA-32 FPU is directly connected to the ALU via internal bus.
False
The REP prefix checks the value of ECX but will not modify it.
False
The REP prefixes may be used with most instructions (MOV, CMP, ADD, etc...).
True
The REPNE prefix checks the value of the Zero flag but requires its operand-instruction (the instruction which follows it) to modify the flag.
PTR
The _________ operator overrides the default type of a label (variable), and can also be used to combine elements of a smaller data type and move them into a larger operand.
LENGTHOF
The _________ operator returns a count of the number of elements in a single data declaration.
SIZEOF
The _________ operator returns a value that is equivalent to multiplying the number of elements in a single data declaration by the size, in bytes, of a single element of a data declaration.
TYPE
The _________ operator returns the size, in bytes, of a single element of a data declaration.
False
The following two instructions are equivalent. RET RET 4
Base + Offset
To access stack-passed parameters in a procedure, which addressing mode is used?
False - Special integers must be converted to floats before they can be on the stack, but this conversion is handled by the FPU instructions beginning with FI
True or False: It is possible to push integer values to the FPU stack.
Clear direction flag - String primitives will decrement ESI/EDI
What does CLD do?
Sets direction flag - String primitives will increment ESI/EDI
What does STD do?
False - CALL and RET are specific to procedures, not macros
When a macro is invoked, the assembler handles the insertion of CALL and RET instructions.
To keep additional usage of the stack within the procedure from invalidating the stack offsets.
When passing procedure parameters on the stack, why are the following lines of code often necessary in a procedure? PUSH EBP MOV EBP, ESP
