CSC 415 Operating System Principles Unit 07

Inverted page tables require each process to have its own page table. Select one: a. True b. False

b. False

Mobile operating systems typically support swapping. Select one: a. True b. False

b. False

Reentrant code cannot be shared. Select one: a. True b. False

b. False

A relocation register is used to check for invalid memory addresses generated by a CPU. Select one: a. False b. True

a. False

Fragmentation does not occur in a paging system. Select one: a. False b. True

a. False

There is a 1:1 correspondence between the number of entries in the TLB and the number of entries in the page table. Select one: a. True b. False

b. False

Given a logical address of 0x8E7 and a page size of 256 bytes and given the page table below, what is the physical address (in hex)? Page TableFrameValidity Bit0x9v0x14v0xAv0x21v0x2v0x7v0xCv0x22v0x24v0x27i0x23v0x1i0i0i0i

0x24E7

Given the logical address 0x89457A7C (in hexadecimal) with a offset (displacement) size of 12 bits, what is the page number (in hex)?

0x89457

Assume a system has a TLB hit ratio of 90%. It requires 15 nanoseconds to access the TLB, and 85 nanoseconds to access main memory. What is the effective memory access time (in nanoseconds) for this system?

108.5 Remember that every memory access is 85 nanoseconds. So it will take at least that long, plus the overhead of the paging table. That is what you want to calculate. With no TLB, then it would be 2 memory accesses of 170 nanoseconds.

Given the logical address 0x478D7A5B (in hexadecimal) with a page size of 256 bytes, what is the page offset?

5B

Given the logical address 0x478D7A5B (in hexadecimal) with a offset (displacement) size of 12 bits, what is the page offset?

A5B

Given the logical address 0xAEF9 (in hexadecimal) with a page size of 256 bytes, what is the page offset? A) 0xAE B) 0xF9 C) 0xA D) 0xF900

B) 0xF9

Professor Bierman clearly hates this area of operating systems. Select one: True False

False

Standard swapping involves swapping in pages of processes instead of entire processes. True False

False

The x86-64 bit architecture only uses 48 of the 64 possible bits for representing virtual address space. True False

True

Which of the following technique is well suited to support very large address space, e.g. 64-bit address space? Select one: a. Hierarchical page tables b. Clustered page tables c. All of the above d. Inverted page tables

b. Clustered page tables

Which of the following is true of compaction? Select one: a. It is possible only if relocation is dynamic and done at execution time. b. It can be done at assembly, load, or execution time. c. It cannot shuffle memory contents. d. It is used to solve the problem of internal fragmentation.

a. It is possible only if relocation is dynamic and done at execution time.

Given the logical address 0xAEF9 (in hexadecimal) with a page size of 256 bytes, what is the page number? Select one: a. 0xAE b. 0xF9 c. 0xA d. 0x00F9

a. 0xAE

Consider a 32-bit address for a two level paging system with an 8KB page size. The outer table has 1024 entries. How many bits are used to represent the second-level page table? Select one: a. 9 b. 10 c. 8 d. 12

a. 9

_____ is the method of binding instructions and data to memory performed by most general-purpose operating systems. Select one: a. Execution time binding b. Load-time binding c. Interrupt binding d. Compile time binding

a. Execution time binding

A 32-bit logical address with 8 KB page size will have 1,000,000 entries in a conventional page table. Select one: a. False b. True

a. False

Which of the following is not a reason explaining why mobile devices generally do not support swapping? Select one: a. Small size of mobile applications do not require the use of swap space. b. Limited space constraints of flash memory. c. Limited number of writes of flash memory. d. Poor throughput between main memory and flash memory.

a. Small size of mobile applications do not require the use of swap space.

In the video, Professor Bierman explains the older Intel architecture that had a 16 bit segment register and a 16 bit address register. Check all the statements below that are true. Select one or more: a. The segment register's reference memory on even 16 byte boundries. b. The total of the address space of the segment register and the address register was 20 bits. c. The total of the address space of the segment register and the address register was 24 bits. d. The segmentation of memory was hard to understand even for programmers of the time using it. e. The total of the address space of the segment register and the address register was 32 bits.

a. The segment register's reference memory on even 16 byte boundries. b. The total of the address space of the segment register and the address register was 20 bits. d. The segmentation of memory was hard to understand even for programmers of the time using it.

Hashed page tables are commonly used when handling addresses larger than 32 bits. Select one: a. True b. False

a. True

The ARM architecture uses both single-level and two-level paging. Select one: a. True b. False

a. True

A page-table base register stores Select one: a. a pointer to the page table in memory. b. the page size of the page currently being accessed. c. the starting physical address of the frame currently being addressed. d. the starting logical address of the page currently being accessed.

a. a pointer to the page table in memory.

Replacement question: With segmentation in IA-32 architecture, a logical address consists of _____. Select one: a. segment number, GDT or LDT indicator, protection and offset b. segment number, page number, GDT/LDT, protection and offset c. segment number, page number and offset d. segment number and offset

a. segment number, GDT or LDT indicator, protection and offset

External fragmentation is Select one: a. when there is enough total memory space to satisfy a request but the available spaces are not contiguous. b. when the amount of available memory is less than the size of a process. c. when there is some unused memory that cannot be allocated to a process. d. when a process is broken up into smaller parts for memory allocation.

a. when there is enough total memory space to satisfy a request but the available spaces are not contiguous.

Suppose a program is operating with execution-time binding and the physical address generated is 300. The relocation register is set to 100. What is the corresponding logical address? Select one: a. 201 b. 200 c. 300 d. 199

b. 200

Consider a logical address with 18 bits used to represent an entry in a conventional page table. How many entries are in the conventional page table? Select one: a. 1,024 b. 262,144 c. 18 d. 1,048,576

b. 262,144

The x86-64 architecture provides support for Select one: a. 64-bit physical addresses b. 52-bit physical addresses c. 32-bit physical addresses d. 48-bit physical addresses

b. 52-bit physical addresses

Hierarchical page tables are appropriate for 64-bit architectures. Select one: a. True b. False

b. False

Which of the following is true about dynamic storage allocation? Select one: a. First fit is clearly better than best fit in terms of time and storage utilization. b. First fit requires less time for allocation than worst fit on average. c. Worst fit provides the best storage utilization. d. Best fit is clearly better than first fit in terms of time and storage utilization.

b. First fit requires less time for allocation than worst fit on average.

Hashed page tables are particularly useful for processes with sparse address spaces. Select one: a. False b. True

b. True

In swapping with paging technique, individual pages of a process are swapped in or out. Select one: a. False b. True

b. True

Without a mechanism such as an address-space identifier, the TLB must be flushed during a context switch. Select one: a. False b. True

b. True

Replacement Question: Address translation from a logical address to a physical address in IA-32 architecture is comprised of Select one: a. a paging unit followed by a segmentation unit that translates the logical address to its physical address. b. a segmentation unit followed by a paging unit that translate the logical address to its physical address. c. a segmentation unit that translates the logical address to its physical address. d. a paging unit that translates the logical address to its physical address.

b. a segmentation unit followed by a paging unit that translate the logical address to its physical address.

A translation look-aside buffer is used to Select one: a. store the address of the page table in memory. b. cache page table entries. c. store page size. d. size of the logical address space of the currently running process.

b. cache page table entries.

The mapping of a logical address to a physical address is done in hardware by the _____________. Select one: a. relocation register b. memory-management-unit (MMU) c. memory address register d. dynamic loading register

b. memory-management-unit (MMU)

Standard swapping is generally not used in contemporary operating systems, becuase Select one: a. contemporary operating systems fo not oversubscribe memory. b. the amount of time required to move entire processes between main memory and the backing store is prohibitive. c. memory in contemporary systems is large enough to store all processes. d. some processes are so large that they cannot fit in backing store.

b. the amount of time required to move entire processes between main memory and the backing store is prohibitive.

Reentrant code is easier to share when paging is used, because Select one: a. each process can modify that code its own way. b. the code doesn't change during execution. c. All of the above. d. the code changes are identical for each process.

b. the code doesn't change during execution.

Assume a system uses 2-level paging and has a TLB hit ratio of 90%. It requires 15 nanoseconds to access the TLB, and 85 nanoseconds to access main memory. What is the effective memory access time in nanoseconds for this system? Select one: a. 22 b. 108.5 c. 117 d. 30.5

c. 117

If the base register is loaded with value 12345 and limit register is loaded with value 1000, which of the following memory address access will not result in a trap to the operating system? Select one: a. 12200 b. 12344 c. 12500 d. 13346

c. 12500

Consider a logical address with a page size of 8KB. How many bits must be used to represent the page offset (displacement) in the logical address? Select one: a. 22 b. 8 c. 13 d. 12 e. 10

c. 13

Which of the following statements are true with respect to hashed page tables? Select one: a. Hash table collisions do not occur because of the importance of paging. b. They only work for sparse address spaces. c. A common approach for handling address spaces larger than 32 bit. d. The virtual address is used to hash into the hash table.

c. A common approach for handling address spaces larger than 32 bit.

What is the key advantage of swapping? Select one: a. That you can preserve a process on the hard disk. b. Provides a communication mechanism between a process and the operating system. c. Allows the allocation of more memory then the main memory on the system. d. Provides a communication mechanism between applications. e. Makes loading of applications faster.

c. Allows the allocation of more memory then the main memory on the system.

In a dynamically linked library _________. Select one: a. loading is postponed until execution time b. system language libraries are treated like any other object module c. a stub is included in the image for each library-routine reference d. more disk space is used than in a statically linked library

c. a stub is included in the image for each library-routine reference

Computing systems need cache because Select one: a. All of the about. b. main memory is expensive and cache offsets the cost. c. accessing main memory is slow and cache speeds it up. d. register access is slow and cache speeds it up.

c. accessing main memory is slow and cache speeds it up.

A page address extension (PAE) in IA-32 _______________________. Select one: a. increases address size to 64 bits. b. does not need any operating system support. c. allows 32-bit processors to access a physical address space larger than 4GB. d. introduces two-level paging scheme.

c. allows 32-bit processors to access a physical address space larger than 4GB.

Absolute code can be generated for ____________. Select one: a. execution-time binding b. interrupt binding c. compile-time binding d. load-time binding

c. compile-time binding Binding means that the address is resolved and no longer needs attention beyond that point.

The _____ binding scheme facilitates swapping. Select one: a. load time b. assembly time c. execution time d. interrupt time

c. execution time

The roll out, roll in variant of swapping is used ____. Select one: a. for the round-robin scheduling algorithm b. when the load on the system has temporarily been reduced c. for priority-based scheduling algorithms d. when a backing store is not necessary

c. for priority-based scheduling algorithms

A(n) _________ page table has one page entry for each real page (or frame) of memory. Select one: a. clustered b. forward-mapped c. inverted d. virtual

c. inverted

A 64-bit architecture with more than 16 quintillion addressable memory Select one: a. can support a majority of today's application requirements, but not all. b. All of the above. c. is large enough to support all current application requirements but may not be able to support all future application requirements. d. is large enough to support all current as well as future application requirements.

c. is large enough to support all current application requirements but may not be able to support all future application requirements.

An address generated by a CPU is referred to as a ____. Select one: a. physical address b. post relocation register address c. logical address d. Memory-Management Unit (MMU) generated address

c. logical address

A page out operation Select one: a. deletes a page from the backing store. b. moves a page from one frame to another. c. moves a page from memory to the backing store. d. moves a page from the backing store to memory.

c. moves a page from memory to the backing store.

The protection bit in a page table Select one: a. All of the above. b. marks a frame as read-only or read-write. c. provides protection against unauthorized updates in the page table. d. marks a page table as read-only or read-write.

c. provides protection against unauthorized updates in the page table.

Assume the value of the base and limit registers are 1200 and 350 respectively. Which of the following addresses is legal? Select one: a. 355 b. all of the above c. 1551 d. 1200

d. 1200

A frame table stores Select one: a. which frames are allocated. b. total number of frames. c. which frames are free. d. All of the above.

d. All of the above.

_________ is the dynamic storage-allocation algorithm which results in the smallest leftover hole in memory. Select one: a. Worst fit b. First fit c. None of the other answers d. Best fit

d. Best fit

If the starting address location changes, in which of the following cases, the program has to be recompiled? Select one: a. Load time binding. b. Execution time binding. c. Both compile and load time bindings. d. Compile time binding

d. Compile time binding

Which of the following statement is correct? Select one: a. Any attempt by a user program to access memory at an address higher than the base register value results in a trap to the operating system. b. Base register holds the size of a process. c. Base and limit registers can be loaded by the standard load instructions in the instruction set. d. Limit register holds the size of a process.

d. Limit register holds the size of a process.

_________ is the dynamic storage-allocation algorithm which results in the largest leftover hole in memory. Select one: a. First fit b. None of the other answers c. Best fit d. Worst fit

d. Worst fit

A(n) ______ matches the process with each entry in the TLB. Select one: a. page number b. stack c. process id d. address-space identifier

d. address-space identifier

Suppose the size of a process is 10,000 bytes and the relocation register is loaded with value 5000, which of the following memory address this process can access? Select one: a. physical address 4,500 b. logical address 10,350 c. None of the above d. physical address 10,350

d. physical address 10,350

The x86-64 architecture provides support for Select one: a. three different page sizes using 3-level paging hierarchy. b. four different page sizes using 3-level paging hierarchy. c. four different page sizes using 4-level paging hierarchy. d. three different page sizes using 4-level paging hierarchy.

d. three different page sizes using 4-level paging hierarchy.

Given a logical address of 0x9E7 and a page size of 256 bytes and given the page table below, what is the result of the memory access? Page TableFrameValidity Bit0x9v0x14v0xAv0x21v0x2v0x7v0xCv0x22v0x24v0x27i0x23v0x1i0i0i0i Select one: a. It references physical memory address of 0x27E7. b. It references physical memory address of 0x24E7. c. None of the other answers d. It references physical address 0x24E7 which is not a valid page and causes a page fault. e. It references physical memory address of 0x279E7. f. It references physical address 0x27E7 which is not a valid page and causes a page fault.

f. It references physical address 0x27E7 which is not a valid page and causes a page fault.