digital systems principles and applications Chapter 4; ed. 11 (Ronald Tocci)

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PROCESS

A VHDL keyword that defines the beginning of a block of code that describes a circuit that must respond whenever certain signals (in the sensitivity list) change state. All sequential statements must occur inside process.

selected signal assignment

A VHDL statement that allows a data object to be assigned a value from one of several signal sources depending on the value of an expression.

libraries

A collection of descriptions of commonly used hardware circuits that can be used as modules in a design file.

ELSIF

A control structure that can be used multiple times following an IF statement to select one of several options in describing a circuit's operation based on whether the associated expressions are true or false.

IF/THEN

A control structure that evaluates a condition and performs an action if the condition is true or bypasses the action and continues on if the condition is false.

CASE

A control structure that selects one of several options when describing a circuit's operation based on the value of a data object.

ELSE

A control structure used in conjunction with IF/THEN to perform an alternate action in the case that the condition is false. An IF/THEN/ELSE always performs one of two actions.

top-down

A design method that starts at the overall system level and then defines a hierarchy of modules.

programmer

A fixture used to apply the proper voltages to PLD and PROM chips in order to program them.

Karnaugh Map (K map)

A graphical tool used to simplify a logic equation or to convert a truth table to its corresponding logic circuit int a simple, orderly process.

In-System Programmable (ISP)

A means by which a chip does not need to be removed from its circuit board in order to store programming information.

hierarchical design

A method of designing a project by breaking it down into constitutions modules, each of which can be broken further into simpler constituent modules.

don't-care condition

A situation when a circuit's output level for a given set of input conditions can be assigned as either a 1 or 0.

macrofunction

A term used by Altera corporation to describe the predefined hardware descriptions in the their libraries that represent standard IC parts.

concatenate

A term used to describe the arrangement of linking of two or more data objects into ordered sets.

dual-in-line package (DIP)

A very common IC package with two parallel rows of pins intended to be inserted into a socket or through holes drilled in a printed circuit board.

bit array/bit vector

A way to represent a group of bits by giving it a name and assigning an element number to each bit's position. This same structure is somes

zero insertion force (ZIF) socket

Allows for dropping the chip in place and then clamp the contacts onto the pins.

index

Another name for the element number of any given bit in a bit array.

parity checker

Circuit that takes a set of data bits (including the parity bit) and checks to see if it has the correct parity.

parity generator

Circuit that takes a set of data bits and produces the correct parity bit for the data.

Looping

Combining of adjacent squares in a Karnaugh map containing 1s for the purpose of simplification of sum-of-products expression.

logic probe

Digital troubleshooting tool that senses and indicates the logic level at a particular point in a circuit.

concurrent

Events that occur simultaneously (at the same time.)

STD_LOGIC

In VHDL, a data type defined as an IEEE standard. It is similar to the BIT type, but it offers more possible values than just 1 or 0.

STD_LOGIC_VECTOR

In VHDL, a data type defined as an IEEE standard. It is similar to the BIT_VECTOR type, but it offers more possible values than just 1 or 0.

literals

In VHDL, a scalar value or bit pattern that is to be assigned to a data object.

BIT_VECTOR

In VHDL, the data object type representing a bit array.

INTEGER

In VHDL, the data object type representing a numeric value.

floating

Input signal that is left disconnected in a logic circuit.

complementary metal-oxide semiconductor (CMOS)

Integrated-circuit technology that uses MOSFETs as the principal circuit element. This logic family belongs to the category of unipolar digital ICs.

transistor-transistor logic (TTL)

Integrated-circuit technology that uses the bipolar transistor as the principal circuit element.

JEDEC

Joint Electronic Device Engineering Council, which established standards for IC pin assignments and PLD file format.

JTAG

Joint Test Action Group, which created a standard interface that allows access to the inner workings of an IC for testing, controlling, and programming purposes.

sequential

Occurring one at a time in a certain order. In HDL, the circuits that are generated by sequential statements behave differently, depending on the order of the statements in the code.

indeterminate

Of a logic voltage level, outside the required range of voltages for either logic 0 or 1 .

test vectors

Sets of inputs used to test a PLD design before the PLD is programmed.

SSI, MSI, LSI, VLSI, ULSI, GSI

Small scale integration

sensitivity list

The list of signals used to invoke the sequence of statements in a PROCESS.

maxplus2 Function

The name Quartus II uses to describe library functions that emulate TTL standard parts from the 74XX series.

decision control structure

The statements and syntax that describe how to choose between two or more options in the code.

product-of-sums (POS)

These expressions consist of two or more OR terms (sums) that are ANDed together.

sum-of-product (SOP)

These expressions consists of two or more AND terms (products) ORed together.

exclusive-OR (XOR)

This circuit produces a HIGH output whenever the two inputs are at opposite levels.

exclusive-NOR (XNOR)

This circuit produces a HIGH output whenever the two inputs are at the same level.

enable/disable

To reach or not reach the output.

contention

Two (or more) output signals connected together trying to drive a common point to different voltage levels.

objects

Various ways of representing data in the code of any HDL.


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