Introduction to Computer Concepts

You have observed that a conflict has occurred because the two instructions in a program are to be executed in sequence, and both access a particular memory or register operand. Which of the following is referred to in the scenario? A. Software interrupt B. Data abort C. Loop buffer D. Data hazard

Data hazard

During the functioning of the control unit, control signals are emitted to which of the following destinations? A. Sequencing logic, data path, and ALU B. Data path, ALU, and system bus C. Address latch, timing generator, and decoder D. Instruction register, system bus, and decoder

Data path, ALU, and system bus

Ron, an instructional designer, wants to determine whether string processing instructions increment or decrement the 16-bit half-registers SI and DI or the 32-bit registers ESI and EDI. Which of the following x86 EFLAGS register bits will he use? A. Alignment check B. Identification flag C. Direction flag D. Resume flag

Direction flag

Camilla, a security administrator, wants to keep the stat information of a processor up to date where every local action that can affect the global state of a line must be reported to the central controller. Which of the following protocols will she use? A. Directory B. Snoopy C. MESI D. Update

Directory

Laura, a software designer, wants to design Pentium 4 processor in which the program instructions are collected in order from the L2 cache, then instructions are decoded into a series of micro-operations, and later the results get stored in the L1 instruction cache. Which of the following components will she use? A. Execution units B. Out-of-order execution logic C. Fetch/decode unit D. Memory subsystem

Fetch/decode unit

Why the circuits of NOR based S-R latch are classified as asynchronous sequential circuits?

Functions in the absence of a clock pulse

Which of the following is an electronic circuit that produces an output signal that is a simple Boolean operation on its input signals? A Transistor B Gate C Multichip module D Microelectronic chip

Gate

You want to deal with supercomputers and their software, especially for scientific applications that involve large amounts of data and the use of parallel algorithms. What will you use?

HPC - High-Performance Computing

Your organization is using a standard that enables 62,000 servers, remote storage, and other networking devices that are attached in a central fabric of switches and links. Which of the following the organization is using? A. FireWire B. SCSI C. Thunderbolt D. Infiniband

Infiniband

If the clock cycle is in phase y2, then which of the following R3000 pipeline stages will you use to send the physical address to the instruction address? A. ALU B. Read C. Instruction fetch D. Memory access

Instruction fetch

Which of the following is a desirable characteristic of a benchmark program? A. It has a wide distribution B. It is written in a low-level language C. It is a representative of different kinds of programming domain or paradigm D. It is measured with difficulty.

It has a wide distribution

Your organization is using hexadecimal notation for representing integers. What is the reasoning behind this choice?

It is more compact than binary notation. In most computers, binary data occupy some multiple of 4 bits, and hence some multiple of a single hexadecimal digit. It is extremely easy to convert between binary and hexadecimal notation Expressing MAC addresses in hexadecimal format makes them easier to read and work with.

Joe works as a software engineer at XYZ. His organization has asked to combine one or more files containing object code from separately compiled program modules into a single file containing loadable or executable code. Which of the following will he use? A. Interpreter B. Loader C. Linker D. Compiler

Linker

Which of the following properties can be exploited in the formation of a two-level memory? A. Locality B. Transfer rate C. Inclusion D. Coherence

Locality

What is defined as the time it takes to fetch two operands from registers, perform an ALU operation, and store the result in a register?

Machine Cycle

Which of the following provides very high bit density and very low cost per bit, with relatively slow access time? A. DDR2 SDRAM B. SRAM C. Magnetic disk D. DDR3 SDRAM

Magnetic disk

The transaction layer (TL) supports which of the following address spaces? A. Configuration, Memory, Register, Output B. Message, Fetch, Execute, I/O C. Memory, I/O, Configuration, Message D. Configuration, Message, I/O, Execute

Memory, I/O, Configuration, Message

An input signal is allowed to pass through a gate, which in turn produces an inverted output. Which of the following logic gates is used? A. NOT B. NOR C. AND+NOR D. XOR

NOT

Which of the following consists of shifting significand digits left until the most significant digit (bit, or 4 bits for base-16 exponent) is nonzero? A. Normalization B. Standardization C. Rounding D. NaN

Normalization

Which of the following factors will you consider in determining the use of the addressing bits?

Number of addressing modes & Address range

What will you use in scalar RISC processors to improve the performance of instructions that require multiple cycles?

Out-of-order completion

You have observed that an interruption has occurred when the page containing a referenced word was not in the main memory. Which of the following is referred to in the scenario? A. Segmentation B. Page fault C. Demand paging D. Page Write Through bit

Page fault

In which of the following clustering methods does a secondary server take over in case of primary server failure? A. Passive standby B. Servers connected to disks C. Separate servers D. Active secondary

Passive standby

Which of the following methods is suitable for programming on a computer to give an automatic tool for producing minimized Boolean expressions? A. Quin-McCluskey B. Gradient descent C. Newton-Raphson D. Runge-Kutta

Quin-McCluskey

Sophie, an instructional analyst, runs the following instructional code to move the contents of the AX register to the CX register: MOV AX, CX What type of addressing has she performed?

Register

You have observed that two or more instructions are competing for the same memory at the same time. Which of the following is referred to in the scenario? A. Procedural dependency B. Resource conflict C. Out-of-order completion D. Instruction issue

Resource conflict

Erika wants to perform push, pop, and other stack instructions by ensuring that the instructions do not contain an explicit stack operand. Which of the following registers will she use? A. SP B. MAR C. Segment D. Index

SP

Which of the following SPEC suites is a standard for measuring 3D graphics performance based on professional applications? A. SPECjvm2008 B. SPECsfs2014 C. SPECviewperf D. SPEC Cloud_IaaS

SPECviewperf

During the functioning of a microprogrammed control unit, which of the following loads a new address into the control address register based on the next-address information form the control buffer register and the ALU flags? A. Sequencing logic unit B. Hardwired control unit C. Control instruction register D. Arithmetical unit

Sequencing logic unit

Sophia, a system engineer, has added two negative numbers, but an overflow condition has occurred. Which of the following reasons is responsible for this? A. The result has the opposite sign B. Their sum is a prime number C. The result is larger than the number D. The result has the same sign

The result has the opposite sign

Which of the following hardware features is set at the beginning of each job and prevents a single job from monopolizing the system? A. Interrupts B. Timer C. Memory protection D. Privileged instructions

Timer

Alicia works as a software engineer at XYZ. She has placed multiple words in a single cache block. What is her reasoning behind this course of action?

To exploit spatial locality of reference in a program

Which of the following control lines indicates that data have been accepted from or placed on the bus? A. Memory read B. Transfer ACK C. Interrupt ACK D. Clock

Transfer ACK

You are asked to calculate the minimum number of disks required for RAID1. Which of the following is the result of your calculation? A. One B. Four C. Two D. Six

Two

For which of the following purposes does the processor issue a signal to the bus of read-with-intent-to-modify (RWITM)? A. Write miss B. Write-buffer C. Write-allocate cache D. Write hit

Write miss

Laura, an instructional designer, wants to define multi-line macros. Which of the following mnemonics will she use? A. %MACRO% B. %MACRO C. #MACRO D. &MACRO

%MACRO

You are asked to calculate the hexadecimal value of the number (254)10. What is your answer?

(FE)16

Which of the following is an SRAM? A. 1 T-RAM B. PROM C. Hard Disk D. EPROM

1 T-RAM

You have observed that a disk of your digital camera is rotating at a constant speed with 5s latency time, 8s transfer time, and 4s seek time. What is the block access time of the disk?

17s

Your organization is using ARM machines to encrypt data for security. Each instruction is encoded into how many bytes of word?

4

Your organization is using a wireless mesh network that provides signaling rates of up to 11 Mbps. Which IEEE 802.11 standard is your organization using? A. 802.11a B. 802.11n C. 802.11b D. 802.11g

802.11b

Which of the following status bits represent carrying or borrowing between half-bytes of an 8-bit arithmetic or logic operation? A. S B. A C. C D. P

A

If the DMA module is transferring a block of data from memory to disk, then which of the following will the DMA module perform? A. The DMA increments the counter and decrements the address pointer and repeats this process until the count reaches zero and the task is finished/ B. A peripheral device will request the service of the DMA by pulling DMA request (DREQ) high. C. The DMA will put a low on its hold request (HRQ) D. The DMA will deactivate DMA acknowledge (DACK)

A peripheral device will request the service of the DMA by pulling DMA request (DREQ) high.

Which of the following supports coherency between Cortex-A15 and Cortex-A7 processors by enabling ARM big.LITTLE technology? A. DSP B. GIC C. ACE D. SMT

ACE

Which of the following is the name of the CPU register in a single-address instruction format and is implicitly one of the two operands for the instruction?

Accumulator

In which of the following ways does the generic interrupt controller (GIC) route an interrupt to one or more CPUs? A. An interrupt can be directed to a specific processor only. B. An interrupt can be directed to programmable events. C. An interrupt can be directed to only private processors D. An interrupt can be directed to an undefined group of processors.

An interrupt can be directed to a specific processor only.

Whenever a branch instruction is encountered in the instruction stream, what is checked?

BTB

Maria, a system analyst, wants to send data to the I/O module (INPUT or READ), report status, or perform some control function particular to the device. Which of the following will she use? A. Power signals B. Status signals C. Control signals D. Signal relays

Control signals

Which of the following instructions changes the format or operates on the format of data? A. Input/output B. System control C. Branch D. Conversion

Conversion

In which of the following, the binary floating-unit part handles all binary and hexadecimal floating-point operations?

VFU