IT 254 Final

Briefly describe four advantages of clustering computers

1) Increases the available computing power by combining the power of the individual systems. 2) Clustering is used to create fault tolerant systems. 3) Clustering is used to create high-availability systems. 4) Clustering is used for load-balancing systems with large workloads.

Thunderbolt is designed to support a data transfer rate of up to ___ gigabits per second in each direction through each of two channels, which is suitable for the transfer of full high definition video with sound.

10

USB-3 is capable of a full duplex data transfer rate up to _____ gigabits per second, which makes it suitable for use with a wide range of devices.

10

If the Memory address register is 8 bits wide, the number of possible memory addresses is

256

Thunderbolt connections can be made using either copper or fiber optic cable. The optic cable will work over distances of up to ______ meters.

50

Cache memory hit ratios of ________ percent and above are common with just a small amount of cache.

90

Each block of cache memory provides a small amount of storage, perhaps between 8 and 64 bytes, also known as

A cache line

Explain the basic differences between grid computing and cluster computing

A cluster is a group of loosely coupled computers configured to work together as a unit; each computer in a cluster is a complete unit, with its own CPU, memory, and I/O facility. Grid computing systems use the spare processing capacity of computers connected to a network. Each computer is given a small portion of the task to process in its spare time.

Which of the following is an example of an interrupt being used as an external event notifier?

A keyboard input

The INPUT instruction takes data from the

A mailbox from the calculator

The SUBTRACT instruction subtracts data in

A mailbox from the calculator

The ADD instruction adds data from

A mailbox to the calculator

A bus line that is "one-way" is called

A simplex bus line

Which of the following is not a function of how interrupts are used?

A way of buffering large amounts of data

Events related to problems or special conditions within the computer system itself, like divide by zero, or attempting to execute a nonexistent op code, are called

Abnormal Events

The different ways of establishing memory addresses within an instruction are called

Addressing Modes

Interrupts are normally checked

After one instruction is finished and before another begins

The primary purpose of channel programs is to transfer data using DMA between

An I/O device and memory

The area inside of the CPU that holds data temporarily and performs calculations is called the

Arithmetic logic unit

How is an arithmetic overflow error or divide by zero error interrupt different than an interrupt from the hard disk controller signaling that a data transfer has completed? (Three or four sentences are sufficient)

Arithmetic overflow or divide by zero errors are abnormal events and it may not be possible to complete the program in execution. In that case, the OS attempts to gracefully recover from the error through traps or exceptions. A hard disk controller interrupting the CPU to signal that a data transfer has completed is used by the OS to resume control of the program requesting the data transfer and does not create the possibility that the system is halted.

The determining factor that distinguishes a loosely coupled system is the ______________ of each computer within the system complex or network.

Autonomy

The Little Man instruction set is based on a decimal number system; real computers encode instructions and data using the

Binary System

Data from disks, and tapes, and flash memory are transferred only in

Blocks of data

Some systems provide a small amount of dedicated memory built into the CPU that maintains a record of previous choices for each of several branch instructions that have been used in the program being executed to aid in determining whether a branch is likely to be taken. What are the contents of this memory called?

Branch history table

Blade servers are computers mounted on a board similar to a motherboard that can be plugged into connectors on a rack. The blades themselves are

Built from standard off-the-shelf parts.

The physical connections that make it possible to transfer data from one location in the computer system to another are called

Buses

The ALU and CU together are known as the

CPU

The OUTPUT instruction takes data from the

Calculator and places it in the out basket

The BRANCH ON POSITIVE instruction "jumps" if the value in the

Calculator is positive

The BRANCH ON ZERO instruction "jumps" if the value in the

Calculator is zero

The STORE instruction copies data from the

Calculator to a mailbox

In the channel architecture, used on IBM mainframes, the I/O processor acts as a separate computer just for I/O operations, thus freeing the computer CPU for other tasks. This I/O processor has its own set of instructions known as ____________, and executes them independently of the CPU.

Channel control words

The input-output architecture based on separate I/O processors and used on IBM mainframes

Channel subsystem

Loading the value zero into a register is called

Clearing a register

The __________ must be designed to assure that each step of the instruction cycle has time to complete before the results are required by the next step.

Clock Cycle

The method of connecting loosely coupled computers together with a dedicated communication channel or link that passes messages between machines is called

Clustering

Nearly all supercomputing capability is based on

Clustering technology

Each CPU in the processor, within a single integrated chip, is called a ___________

Core

The fetch unit portion of the CPU consists of an instruction fetch unit and an instruction ____________ unit.

Decode

Blade servers are computers mounted on a board similar to a motherboard that can be plugged into connectors on a rack. A typical blade server has one or more

Dedicated hard drives

Since many interrupts exist to support I/O devices, most of the interrupt handling programs are also known as

Device Drivers

I/O controllers that control a single type of device are often called

Device controllers.

An I/O technique that transfers block data directly between the I/O controller and computer memory, is called

Direct memory access

A part of main memory can be allocated to store several adjoining blocks of disk memory. If the requested data is in _________ then no disk access is necessary.

Disk cache

An I/O controller that is designed to control hard disks is called a

Disk controller

An important difference between the I/O requirements of keyboards and disk drives is that

Disk data is always transferred in blocks, never as individual bytes as with the keyboard

Beowulf clusters are simple, highly configurable clusters designed to provide high performance at low cost. Beowulf clusters consist of multiple computers connected together by a dedicated, private

Ethernet

The ___________ unit contains the arithmetic/logic unit and the portion of the control unit that identifies and controls the steps that comprise the execution part for each different instruction.

Execution

Clustering can be used to create fault tolerant systems, because, if a node were to fail, software controlling the cluster can simply switch processing to other nodes in the cluster, an operation called

Failover

Optical conductors are

Faster than electrical conductors

The instruction cycle can be broken into these two parts

Fetch and execute

The first step in the instruction cycle is

Fetch the instruction from memory

The IEEE 1394 bus is sometimes referred to as

Firewire

The 1-bit registers that are used to allow the computer to keep track of special conditions (like overflow or power failure) are often called

Flags

Branch instructions must always be processed ahead of subsequent instructions. Conditional branch instructions are more difficult than unconditional branches. These types of dependencies are known as control dependencies or sometimes as ______________ or branch dependencies.

Flow

What is the primary gateway bus from CPU chip to peripheral controllers?

From the text "For most current personal computer motherboard designs, the PCI-Express bus has assumed predominance as the primary gateway bus of choice from the CPU chip or I/O bridge to the various peripheral controllers."

What common device will eSATA support?

From the text, "A variation, eSATA, extends the SATA bus to support external storage drives."

Devices like printers, modems, mice, disk drives, DVD-ROMs, graphics scanners, and video cameras are commonly connected to the computer system through one of several high-speed general interface bus ports. List some of the interface bus ports in common use.

From the text, "Interface buses in common use for this purpose include USB, SCSI, SATA, Thunderbolt, and IEEE 1394 buses."

Super-scalar processing complicates the design of a CPU considerably. There are a number of difficult technical issues that must be resolved to make it possible to execute multiple instructions simultaneously. What are the most important issues?

From the text: Problems that arise from instructions completing out of order Changes in program flow due to branch instructions Conflicts for internal CPU resources, particularly general-purpose registers

What would be the limitation of having a single system bus that connected the CPU, memory and all the various modules that control I/O devices?

From the text: "....... this approach would subject the overall performance of the system to the limited bandwidth of a single bus. More commonly, the system bus in a bus architecture connects through one or more bus interface circuits to a number of different interconnected buses."

Increasing the number of CPUs is usually an effective way to improve performance although, as the number of CPUs increases, the value of the additional CPUs diminishes. Why is that?

From the text: "...because of the overhead required to distribute the instructions in a useful way among the different CPUs and the conflicts among the CPUs for shared resources, such as memory, I/O, and access to the shared buses. With the exception of certain, specialized systems, there are rarely more than sixteen CPUs sharing the workload in a multiprocessing computer; more commonly today, a multiprocessor might consist of two, four, or eight core CPUs within a single chip."

What are three important CPU architectural families, today?

From the text: "At present, important CPU architectural families include the IBM mainframe series, the Intel x86 family, the IBM POWER/PowerPC architecture, the ARM architecture, and the Oracle SPARC family."

What are blade servers?

From the text: "Blade components, often called blade servers, are computers mounted on a board similar to a motherboard that can be plugged into connectors on a rack....a typical blade has one or more multiple-core CPUs, memory, I/O options, including Ethernet capability, and, often, one or two dedicated hard drives for local access on the blade."

How does the cache controller know when to use cache or go to main memory?

From the text: "Every CPU request to main memory, whether data or instruction, is seen first by cache memory. A hardware cache controller checks the tags to determine if the memory location of the request is presently stored within the cache."

Describe the technique called code-morphing.

From the text: "Furthermore, a technique called code-morphing can be used to translate complex variable-width instruction words to simpler fixed-width internal equivalents for faster execution. This technique allows the retention of legacy architectures while permitting the use of modern processing methods. Modern x86 implementations use this approach."

Summarize how separating the fetch-execution cycle into different fetch and execution units improves performance.

From the text: "Implementation of the fetch-execute cycle is divided into two separate units: a fetch unit to retrieve and decode instructions and an execution unit to perform the actual instruction operation. This simple reorganization of the CU and ALU components allows independent, concurrent operation of the two parts of the fetch-execute cycle."

What would happen if interrupts were checked and processed during the middle of an execution cycle instead of after the execution cycle has completed? (Two or three sentences should be adequate to answer this question)

From the text: "Interrupts are normally checked at the completion of each instruction. That is, interrupts are normally checked after one instruction is finished and before another begins. This assures that conditions won't change in the middle of an instruction that would affect the instruction's execution."

What are some of the research issues related to grid computing given in the text?

From the text: "Issues include effective division of the workload, scheduling work, preventing interference with local processing, effective use of the results, and security and privacy for the client machines."

Once a DMA transfer has been initiated, why is it important that data being transferred not be modified during this period? (Two or three sentences should be adequate to answer this question)

From the text: "Once the DMA transfer has been initiated, the CPU is free to perform other processing. Note, however, that the data being transferred should not be modified during this period, since doing so can result in transfer errors, as well as processing errors."

How are PCI-Express and USB protocols similar to network protocols?

From the text: "PCI-Express uses a switch similar to that found in Ethernet networks to connect lanes together. PCI-Express, USB, Thunderbolt, and FireWire all break messages into packets for transmission across the bus, and protocols that provide the capability to access the bus, to identify and reconstruct messages, and prevent conflict."

Having large numbers of specialized instructions inhibited efficient organization of the CPU. Why?

From the text: "Specialized instructions were used rarely, but added hardware complexity to the instruction decoder that slowed down execution of the other instructions that are used frequently.

How does the isochronous data transfer technique work for USB devices?

From the text: "The USB protocol allows packets to be scheduled for delivery at regular time intervals. This technique is known as isochronous data transfer."

Describe how the computer uses interrupts to control the flow of data to the printer.

From the text: "The computer sends one block of data at a time to the printer. The size of the block depends on the type of printer and the amount of memory installed in the printer. When the printer is ready to accept more data, it sends an interrupt to the computer. This interrupt indicates that the printer has completed printing the material previously received and is ready for more."

Summarize the principle of "locality of reference"?

From the text: "The locality of reference principle states that at any given time, most memory references will be confined to one or a few small regions of memory."

Summarize the performance benefits of using separate execution units for different types of instructions.

From the text: "The model provides separate execution units for different types of instructions. This makes it possible to separate instructions with different numbers of execution steps for more efficient processing. It also allows the parallel execution of unrelated instructions by directing each instruction to its own execution unit."

Summarize how pipe-lining improves performance.

From the text: "The model uses an assembly line technique called pipe-lining to allow overlapping between the fetch-execute cycles of sequences of instructions. This reduces the average time needed to complete an instruction." Or "Pipelining allows several instructions to be 'in flight' at the same time."

What is the benefit of having fixed-length instructions over variable-length instructions?

From the text: "The use of fixed-length, fixed-format instruction words with the op code and address fields in the same position for every instruction would allow instructions to be fetched and decoded independently and in parallel. With variable-length instructions it is necessary to wait until the previous instruction is decoded in order to establish its length and instruction format."

What are common characteristics included in the instruction set architecture (ISA)?

From the text: "These characteristics include such things as the number and types of registers, methods of addressing memory, and basic design and layout of the instruction set."

) A program in execution generates an interrupt with low priority. Before that interrupt is handled, it generates a high priority interrupt. Discuss how these two interrupts change the flow of execution from the start of the low priority interrupt through the completion of interrupt handling for this sequence of interrupts. (Three or four sentences are sufficient)

From the text: "This [multiple interrupt problem] leads to a hierarchy of interrupts, in which higher-priority interrupts can interrupt other interrupts of lower priority, back and forth, eventually returning control to the original program that was running."

If a cache block is altered, what methods are used to update main memory? Of the various methods, which is faster?

From the text: "Two different methods of handling the process of returning changed data from cache to main storage are in common use. The first method, write through, writes data back to the main memory immediately upon change in the cache. This method has the advantage that the two copies, cache and main memory, are always kept identical. Some designers use an alternative technique known variously as store in, write back, or copy back. With this technique, the changed data is simply held in cache until the cache line is to be replaced." Or "The write back method is faster"

A bus line that can carry data in both directions at the same time is called a

Full duplex bus line

Systems that use the spare processing capacity of computers connected to a network is called

Grid computing

Out-of-order instruction execution can cause problems because a later instruction may depend on the results from an earlier instruction. This situation is known as a __________ or a _______________.

Hazard, dependency

USB uses a _________________ connection system, in which hubs are used to provide multiple connection points for I/O devices.

Hierarchical

Power failures, internal time-sensitive events, or external events that are time sensitive will trigger interrupts that are

High priority events.

DisplayPort was originally designed for

High resolution video displays

Devices that can be added and removed at any time without powering down the system are known as __________ devices

Hot pluggable

Simultaneous thread multiprocessing (STM) is also known as ___________

Hyperthreading

Discuss how writing a device driver for a hard disk would require an in-depth understanding of how the hardware functions. Would you also need an in-depth understanding of the OS platform for which the device was designed to function? (Recommend using over 100 words to adequately answer this question)

I/O controllers work at the CPU interface and the device interface. The I/O device controller must understand the specific OS instructions for CPU interfacing tasks: accepting I/O commands from the CPU, transferring data between the controller and the CPU or memory, and sending interrupts and status information to the CPU. At the device interface, the I/O controller must be able to control the device, such as moving the mechanical read/write head to the correct track in a disk drive, when to read or write data on the track, and maintaining rotational speed of the disk. Thus, writing a device driver would require an in-depth understanding of the OS and hardware.

The mnemonic for the x86 architecture instruction that simulates an interrupt is

INT

The register that holds the current instruction is called the

IR

In Symmetrical Multiprocessing (SMP) each CPU has

Identical access to the operating system, and to all system resources, including memory.

Suppose an application program has initiated a DMA transfer from an I/O device, why does the I/O device controller interrupt the CPU when it's complete? (Two or three sentences should be adequate to answer this question)

In DMA transfers, the CPU is performing other tasks while the data transfer takes place; the CPU is unaware of when the data transfer has completed. The device controller has to notify the CPU when it's done so the interrupt handler can return control to the application that initiated the request.

The incompatibilities in speed between the various devices and the CPU make I/O synchronization difficult, especially if there are multiple devices attempting to do I/O at the same time. To handle these problems data is usually stored

In a buffer

Programs that execute without privileges are said to execute

In user space

Which of the following is not a reason to create clusters of computers?

Increased security

Increasing the number of bits available for the op code in an instruction word

Increases the number of instructions available in the instruction set

What is a "thread"?

Independent segments of programs available to be executed in parallel

The use of fixed-length, fixed-format instruction words with the op code and address fields in the same position for every instruction would allow instructions to be fetched and decoded

Independently and in parallel

Under ideal conditions, each CPU processes its own assigned sequence of program instructions

Independently of other CPUs

Which sequence of commands is needed to enter two numbers into the LMC (using the INPUT command)?

Input, Store, Input

CPU architecture is defined by the basic characteristics and major features of the CPU. "CPU architecture" is sometimes called

Instruction set architecture

There are a number of difficult technical issues that must be resolved to make it possible to execute multiple instructions simultaneously. One of the most important of these is

Instructions completing out of order.

After interrupting a program in execution, and saving the program's context, the computer then branches to a special program known as the

Interrupt handler program

The program that determines the appropriate course of action in the event an interrupt occurs is called the

Interrupt handler.

Computers provide interrupt capability by providing one or more special control lines to the central processor known as

Interrupt lines

External events like keyboard input, mouse clicks, printer "out of paper" messages, and power failures are handled by

Interrupts

The method used to communicate events that need special attention to the CPU are known as

Interrupts

From the perspective of a computer, the network

Is just another I/O device.

Flash Memory

Is nonvolatile

The USB protocol allows packets to be scheduled for delivery at regular time intervals. This technique is known as

Isochronous data transfer

Which of the following is most likely:

L1 cache has 32KB and L2 cache has 1MB

The PCI-Express is made up of a bundle of thirty-two serial, bidirectional point-to-point buses. Each bidirectional bus is called a(n)

Lane

As an alternative approach to multiprocessing systems, several autonomous computers can be tied together through a data communications link where each system can share data and exchange information within the system complex. This approach is called

Loosely coupled systems

The register that holds the address of the memory location that needs to be accessed is called the

MAR

There would never be a reason for an address transfer from the ________ to another register within the CPU.

MAR

The register that will hold the data value that is being transferred between the CPU and a particular memory location is called the

MDR

When the instruction being executed is to store data, the data will be transferred from another register in the CPU to the _____, and from there it will be transferred into memory.

MDR

SATA stands for Serial Advanced Technology Attachment; it replaces an older standard, IDE (Integrated Drive Electronics), and is used primarily as an interface for

Magnetic and optical disk storage devices.

The LOAD instruction copies data from the

Mailbox to the calculator

Interrupts that can be temporarily disabled by program instructions are called

Maskable

The mailboxes in the LMC model are the equivalent to a real computer's

Memory

Another method for increasing the effective rate of memory access is to divide memory into parts, called, _____________ so that it is possible to access more than one location at a time.

Memory interleaving

What is the major drawback of Dynamic RAM (DRAM)?

Memory latency

Explain why it is better to have an I/O device initiate an interrupt to the CPU rather than the CPU monitor the I/O device. (Two or three sentences should be adequate to answer this question)

Monitoring I/O devices is considered polling, which is inefficient for the CPU. By having the I/O device initiate communication to the CPU through an interrupt, it frees the CPU to perform other tasks.

What does "locality of reference" mean?

Most memory references are confined to one or a few small regions of memory

In most computer systems, the CPU, memory, and other major components are mounted to wiring on a printed circuit board known as a(n)

Motherboard

Computers that have multiple CPUs within a single computer, sharing some or all of the system's memory and I/O facilities, are called______________, or sometimes tightly coupled systems.

Multiprocessor systems

Do pipelining and superscalar processing techniques affect the number of clock cycles of any individual instruction? Explain your answer.

No they do not. From the text: "It is important to remember that pipelining and superscalar processing techniques do not affect the cycle time of any individual instruction. An instruction fetch-execute cycle that requires six clock cycles from start to finish will require six clock cycles whether instructions are performed one at a time or pipelined in parallel with a dozen other instructions. It is the average instruction cycle time that is improved by performing some form of parallel execution."

In a cluster of loosely coupled computers, each computer in the cluster is called a

Node

Interrupts that can never be temporarily disabled by program instructions are called

Nonmaskable

Memory that retains its values when power is removed is called

Nonvolatile

The CPU and memory are interconnected through a memory bridge sometimes called the

Northbridge

The sources and destinations of data for an instruction are known as

Operands

A LOAD command will leave the original data in the calculator

Overwritten

A STORE command will leave the original data in the mailbox

Overwritten

An INPUT command will leave the original data in the calculator

Overwritten

Virtually every bus internal to the CPU is

Parallel

A bus in which there is an individual line for each bit of data, address, and control is called a

Parallel Bus

The locality of reference principal makes sense because most of the instructions being executed at a particular time are

Part of a small loop or a small procedure or function

Instructions, fetched from memory, are _____________within the instruction unit, to determine the type of instruction that is being executed. This allows branch instructions to be passed quickly to the branch processing unit for analysis of future instruction flow.

Partially decoded

When clustering is used to connect computing systems, using shared disks, the workload can be divided by partitioning the data between the nodes so that work requests made of each node will be relatively independent and approximately equal. The primary difficulty with this configuration is that it is not always possible to plan for and predict accurately the

Partitioning

The COFFEE BREAK (HALT) instruction

Pauses the program

Which of the following is not a requirement for a computer system to handle I/O in a sufficient and effective manner?

Peripheral devices must operate only in block mode.

In a super-scalar CPU, the instruction unit has a(n) ____ to hold instructions until the required type of execution unit is available.

Pipeline

Overlapping instructions—so that more than one instruction is being worked on at a time—is known as the

Pipelining method

A bus that carries signals from a single specific source to a single specific destination is a(n)

Point-to-point bus

The method of continuously checking the various input devices to determine if input data is waiting is called

Polling

The exposed connectors into which external cables can be plugged are often called

Ports

What are the predecessors of the PCI-Express bus?

Predecessors to PCI-Express include PCI, AGP, and PCI-X.

What are the benefits of server virtualization?

Prevent unwanted interactions, such as security breaches; cost effective; isolated work areas to test applications; physical space reduction; lower environmental control costs; quicker roll-out of systems; improved disaster recovery.

Multiple interrupts can be handled by assigning _______ to each interrupt.

Priorities

Instructions that are intended for use by an operating system program, but not by an application program, are called

Privileged instructions

Instructions that only the operating system can execute are called

Privileged instructions

When an interrupt causes temporary suspension of the program in progress, all the pertinent information about the program being suspended, including the location of the last instruction executed, and the values of data in various registers are stored in an area of memory known as the

Process control block

The BRANCH UNCONDITIONALLY instruction changes the value in the

Program counter (also called instruction location counter).

The LMC knows which mailbox contains the next task by looking at the

Program counter (instruction location counter).

The method of transferring data one word at a time from the CPU to a device is called

Programmed I/O.

Clustering is a fundamental technology in the design of high performance computing systems. Which of the following is not a benefit to clustering?

Programming is easier

The computer system provides an internal clock that sends an interrupt periodically to the CPU signaling that it's time to start processing another program or thread. The time between interrupt pulses is known as a(n)

Quantum

Which of the following is not an advantage of adding more than one CPU processor within a single integrated chip?

Reduce resource conflicts.

The storage locations that are used for a particular defined purpose within the CPU are called

Registers

One way to assure that multiple programs do not unintentionally alter another program's files or intermingle printer output is to

Require that all I/O to shared devices be handled by the operating system.

Multimedia applications, like modifying an image, often use

SIMD instructions

The software interrupt is very similar to which type of instruction?

SUBROUTINE JUMP

A(n) _____________ processor is one that can complete an instruction with each clock tick.

Scalar

One of the issues for systems that use the spare processing capacity of computers connected to a network is

Security and privacy for the client machines

Caching recently used data and instructions is an important performance enhancement. Summarize the benefits cache.

Selected from the subsection on Cache Memory: Main memory access is fast, but still slower than the speed of the CPU. By storing recently used data and instruction in cache, the time required to fulfill a memory request is decreased, thereby increasing overall performance. This improvement is significant because cache hit ratios are commonly over 90%.

A bus that transfers data sequentially, one bit at a time using just a single line pair is called

Serial Bus

Explain the basic differences between the shared-nothing model and shared-disk model in clustering computers.

Shared-nothing model: Each computer has its own disks. This method has the advantage that little communication is required between nodes because each node is essentially independent. Shared-disk model: Data may be shared between cluster nodes because of the presence of common data storage that is accessible to every node. This model offers the advantage of easy dynamic workload balancing and, with careful design, high availability, and fault tolerance.

There are two primary models used for clustering, the _________ model, and the _________ model.

Shared-nothing, shared-disk

Instruction reordering makes it possible to provide parallel pipelines, with duplicate CPU logic, so that multiple instructions can actually be executed

Simultaneously

Which of the following is NOT one of the three lines that control the memory cell?

Skew Line

What are the slowest steps in the instruction fetch-execute cycle?

Slowest steps are those that require memory access.

I/O is typically connected using various standard buses, such as SATA, Thunderbolt, and USB, through I/O controllers and PCI-Express buses to an I/O bridge, sometimes called the

Southbridge

Research and report on the clock speeds, L2 cache size, L3 cache, GPU frequency, and I/O bus type in the "Haswell-DT" (quad-core, 22 nm) chip. There are several different models; just pick one to report. Provide the URL, Author (if available) and date accessed.

Specifications will vary depending on the model numbers. Here is Intel® Core™ i7-4770 Processor specifications clock speed - 4 cores 3.4 GHz L2 cache size - 4 x 256 KB L3 cache size - 8MB GPU frequency 350-1200 MHz I/O bus type - Direct Media Interface (DMI)

When a cache miss occurs, however, there is a time delay while new data is moved to the cache. The time to move data to the cache is called _____________ time.

Stall

Which of the following is not a specific execution unit?

Steering unit

Suppose that the keyboard device stored keystrokes in a buffer until it was full then sent the entire buffer for processing. What would be some adverse consequences? (Two or three sentences should be adequate to answer this question)

Student responses could be more creative, but generally, if user input is expected by an application, then the application would stall waiting for the buffer to fill up. If the user wanted to interrupt the computer, as in typing "CONTROL-ALT-DEL," nothing would happen until the buffer was full.

Considering the computer system as a whole allows further advances in performance, which result from system integration. This is known as

Synergy

The circuitry that connects the CPU to memory and to all the various modules that control I/O devices is called the

System Bus

Consider the steps required to write a block of data from a disk to memory. Outline the major sequence of I/O events that must occur to make this possible. (There are three major steps)

Taken from the example in the text. 1) Four pieces of data are sent to disk controller: 1) the location of the block in memory; 2) the location where the data is to be stored on disk; 3) the size of the block 4) and the direction of transfer: Write. 2) The I/O service program sends a "ready" message to the disk controller and the DMA transfer process takes place. 3) After the transfer is complete, the disk controller sends an interrupt to the CPU signaling completion, and the interrupt handler either returns control to the program that initiated the request or notifies the operating system that the program can be resumed.

Why is it so important that the CPU be allowed to do other tasks while waiting for a particular I/O operation to be completed? (Two or three sentences should be adequate to answer this question.)

The CPU is operating at much higher speeds than I/O operations. If the CPU waited for I/O operations, this would be extremely inefficient.

Which of the following is not a common function of an I/O disk controller?

The I/O disk controller manages main memory during the transfer

The northbridge and southbridge chipsets on the motherboard are used to connect different kinds of things. Explain the use of each of the two chipsets.

The Northbridge connects speed-critical components, such as the CPU and memory. The Southbridge connects various standard buses, such as SATA, Thunderbolt, and USB.

Which of the following is not one of the three primary conditions for direct memory access to take place?

The length of time required to transfer the data.

Internal interrupts caused by events related to problems or special conditions within the computer itself are sometimes called

Traps or exceptions

A LOAD command will leave the original data in the mailbox

Unchanged

A STORE command will leave the original data in the calculator

Unchanged

An ADD command will leave the original data in the mailbox

Unchanged

An OUTPUT command will leave the original data in the calculator

Unchanged

When the device generating the interrupt request identifies its address as part of the interrupt, it is called

Vectored interrupt.

A technique called ____________ is where an individual computer system is used to simulate multiple computers, all sharing the same CPU and I/O facilities.

Virtualization

Which of the following is a commonly used approach for improving performance of memory?

Widening the system bus between memory and the CPU.

The system designer of a workstation computer wants to have enough interrupt codes (IRQs) to support 32 different interrupt lines, IRQ0 - IRQ31. How many bits are needed to address all the IRQs? Show your work and how you arrived at the solution.

Without any control or synchronous bits, 2 to the 5th power equal 32. Therefore 5 bits are needed.

There are several factors that determine the number of instructions that a computer can perform in a second. Which of the following is NOT a factor?

Word size

A serial version of Small Computer System Interface is called

iSCSI

CPUs can actually search ahead for instructions without apparent dependencies, to keep the execution units busy. Current Intel x86 CPUs, can search ___________ instructions ahead, if necessary, to find instructions available for execution.

ten to twenty