LOGIC CIRCUITS FINALS REVIEWER
Gated D Latch
- A gated D latch is designed simply by changing a gated SR latch and the only change in the gated SR latch is that the input R must be modified to inverted S. - Gated latch cannot be formed from SR latch using NOR. - There is no possibility for similar input state
Parallel (Synchronous) counters
- All the FFs are triggered simultaneously by the clock input pulses. - All FFs change at same time - J=K= 0, flop maintains value - J=K=0, flop toggles - Most counters are synchronous in computer systems - Can also be made from D flops - Value increments on positive edge
SR latch
- An SR (Set/Reset) latch is an asynchronous apparatus, and it works separately for control signals by depending on the S-state and R-inputs. - Whenever a high input is given to the S-line of the latch, then the output of Q goes high. - In feedback process, the output Q will stay high when S-input goes low once more. - Active high S R - Active low S' R'
Counters
- Are important components in computers. - The increment or decrement by one in response to input. - A register that goes through a prescribed series of states
Flip flop input equations
- Boolean expression which indicate the input to the flipflops
JK Latch
- Both JK latch as well as RS latch is similar - This latch has two inputs J and K - When JK latch inputs are high the output will be toggled
T Latch
- Can be formed whenever JK latch inputs are shortened. - The function of T latch will be: ○ When the input of the latch is high, then the output will be toggled.
Counters with Parallel load
- Can have preset value - Load signal indicated that Data should be loaded into the counter - Clock resets counter to all zeros - Carry output could be used for higher order bits
State diagram
- Circles indicate current state - Arrows point to next state - For X/Y, x is input y is output - Each state has two arrows leaving ○ One for X = 0, One for X = 1
Synchronous sequential circuits
- Clock pulses/clock signal - If all outputs change (affect) with respect to active transition of clock signal. Then that sequential circuit is synchronous. - Outputs of synchronous are in synch with either only positive or only negative edges of clock signal.
Master-Slave D Flip flop
- Consider two latched combined together - Only one C value active at a time - Output changes on falling edge of the clock
Computation in a typical computer
- Control logic often implemented as a f inite state machine (including ROMS). - Datapath contains blocks such as ALUs, registers, tri-state buffers and RAMS. - In a processor chip often a 5 to 1 ratio of data to control logic
Parallel (synchronous) counters
- Controlled by a clock - All flipflops are triggered by a clock signal - Synchronous counters are more widely used in industry
Positive edge triggered JK Flipflop
- Created from D flip flop - J sets - K resets - J=K=1 -> invert output/toggle
Positive edge triggered T flipflop
- Created from D flip flop - T = 0 - keep current - K - resets - T = 1 - invert current
Positive and Negative Edge D Flip flop
- D flops can be triggered on positive or negative edge - Bubble before Clock C input indicates negative edge triggered.
D Latch
- Data latch is an easy expansion to the gated SR latch that eliminates the chance of unacceptable stated of inputs. - The D latch outputs the input of the D when Enable line is high, otherwise output the D input was whether the enable input was last high. - Known as transparent latch. When enable is stated, then the latch is called transparent and signals spread straightly through it since it is not present
Asynchronous sequential circuits
- Does not base on clock pulses/signal. - Level sensitive - Some of all the outputs of a sequential circuit does not change affects with respect to active transition of clock signal.
Flip flops
- Edge sensitive - Store data on Falling or Rising trigger edge. - Can be defined with characteristic functions. Are powerful storage elements ○ Can be constructed from gates and latches
Ripple (asynchronous) counters
- Flipflop output serves as a source for triggering other flipflops - Triggered by initial count signal - Use flipflop output as flop triggers - Do not require a clock signal
Parallel Data transfer
- Flipflops store outputs from combinational logic - Multiple flipflops can store a collection of data - Multiple flops allow for data storage - The basis of computer memory - Combine storage and logic to make a computation circuit.
Analysis with flipflop
- Identify flipflop input equations - Identify output equations - This example has no output
Asynchronous inputs
- J,K are synchronous inputs ○ Effects on the output are synchronized with the CLK input - Asynchronous inputs operate independently of the synchronous inputs and clock. - Allow for clearing and presetting the flipflop output - 0,0 in preset and clear will not be used. - Reset signal R for D flipflop - If R = 0 the output is cleared - This event can occur at any time, regardless the value of the CLK.
State diagram with one input and one mealy output
- Mano text focuses on Mealy machines - State transitions are shown as a function of input and current output
Finite state machines
- Mealy machine - Moore machine
Sequential logic circuits
- Memory elements can have clock signals or not. - Are able to take into account their previous input state as well as those actually present, a sort of "before" and "after" effect involved with sequential circuits. - "present input", "past input" and "past output". - Two state or Bistable devices which can have their output or output set in one of the two basic states.
Output and state equations:
- Next state dependent on previous state Q(t+1) - next state Q(t) - present state
Latches
- Operate with enable signal, which is level sensitive - output depending on level - Bi stable multivibrator. - Can only store 1 bit of data (meaning 0 and 1).
Mealy machine
- Output based on state and present input
Moore machine
- Output based on state only
Sequential circuits
- Output depends on both present state and present inputs - Feedback path is present - Memory elements are required - Clock signal is required - Difficult to design
State diagram with one input & A moore output
- Outputs cannot change during a clock - pulse if the input variables change - Moore machines usually have more states - No direct path from inputs to outputs
Combinational circuits
- Outputs depend only on present inputs - Feedback path is not present - Memory elements are not required - Clock signal not required - Easy to design
Arithmetic Logic Unit (ALU)
- Performs function like Add, Subtract, and Multiply. - Combinational because of Parallel adder (adds 2 bit) - Are important parts of datapaths Example of ALU chip: 74LS382 ○ Has data and control inputs - Two multibit data inputs - Data-out is same bit width as multi-bit inputs (A and B)
Binary ripple counter
- Reset signal sets all outputs to 0 - Count signal toggle output of low order flipflop - Low-order flipflop provides trigger for adjacent flipflop - Not all flops change value simultaneously - Lower order flops change first - Focus on D flipflop implementation
State table
- Sequence of outputs, inputs, and flipflops states enumerated in state table
Gated SR Latch
- Simple extension of an SR Latch. - It gives an enable line that should be driven high before information can be latched. - Control line is necessary, the latch is not synchronous due to the inputs which can alter the output even in the middle of an enable pulse.
Representation of state:
- State equations - State stable - State diagram
Flip flop State
- Stored values inside flipflop - Behavior of clocked sequential circuit can be determined from inputs, outputs and FF state
D Flip-flop
- Stores a value on the positive edge of C. - Input changes at other time have no effect on output. - Is the simplest and most widely used flipflop
Clocked JK Flipflop
- Two data inputs J and K - J - Set - K - reset - If J&K = 1 then toggle output
Datapath I/O
- Two values enter from the left (A and B) Input -> X (Load A) Input -> Y (Load B) A+B -> Y (A + B) + A -> Output
Synchronous UP/DOWN counters
- Up/Down counters can either count up or down on each clock cycle - Up counter counts from 0000 to 1111 and then changes back to 0000 - Down counters counts from 1111 to 0000 then back to 1111 - Counters count up or down each clock cycle - Output changes occur on clock rising edge
MOD-8 counter
3 bit ripple counter
Type of Modulus:
A. 2 bit up or down (MOD-4) B. 3 bit up or down (MOD-8) C. 4 bit up or down (MOD-16)
2 Types of sequential circuits
Asynchronous sequential circuits Synchronous sequential circuits
Design of a sequence detector
Design of a circuit that detects a sequence of three or more consecutive 1's in a string of bits coming through an input line serial bit stream.
Memory elements
Devices that are capable of storing binary information within them. The binary information stored in the memory elements at a given times define the state of the circuit.
Asynchronous counters
Each ff - output drives the CLK input of the next FF - FFs do not change states in exact synchronism with the applied clock pulses - There is a delay between the responses of successive FFs - Ripple counter due to the way FFs respond to one after another in a kind of rippling effect.
Module N counter
In general, an N bit counter
Sequential circuit
Is specified by time sequence of input, outputs and internal states.
Two basic types of memory elements:
Latches and Flip flops made up of NAND and NOR gate
Modulus counter (MOD-N counter)
MOD-4 counter MOD-8 counter module N counter - MOD number = 2n
Two main types of counters:
Ripple (asynchronous) counters Parallel (synchronous) counters
Different types of Latches:
SR latch Gated SR Latch D Latch Gated D Latch JK Latch T Latch
Classification of sequential logic:
Sequential logic circuits can be constructed to produce either simple edge triggered flipflops are more complex sequential circuits such as storage registers, shift registers, memory devices or counters.
Clock driven
Synchronous circuits that are synchronized to a specific clock signal.
MOD-4 counter
The 2 bit ripple counter
Exicitation Tables
The design of a sequential circuit with flip-flops other than the D type is complicated by the fact that the input equations for the circuit must be derived indirectly from the state table.
Pulse driven
Which is a combination of the two that responds to trigger pulses.
N-bit binary counter
consists of n flip-flops that can count in binary from 0 to 2^n-1
We use synchronous sequential circuit
in synch counters, flip flops, and in the design of MOORE-MEALY state management machines.
Present state
indicates current value of flipflop
Next state
indicates state value after next rising clock edge
Memory Elements
latches, flipflops and counters
Event driven
- Asynchronous depends on previous events. - Asynchronous circuits that change state immediately when enable.
Clocked sequential circuits
- Contain flipflops
Binary counter
- Counter that follows a binary sequence - N bit binary counter counts in binary from n to 2^n-1 - Can be ripple or synchronous
Clocked D Flip flop
- Stores a value on the positive edge of C - Input changes at other times have no effects on output
Two types of input to the combinational logic:
External input Internal input
Output
is the output value on the current clock edge
Internal input
which as functions of a previous output state
External input
which come from outside the circuit design which are not controlled by the circuit
