Operating Systems I - Chapter 1

I/O Techniques

Three techniques: Programmed, Interrupt-Driven, Direct Memory Access.

Interrupt-Driven I/O Drawbacks

Transfer rate is limited by I/O device and processor speed. Processor is tied up in handling I/O data/instructions.

Multiple Interrupts

Two approaches: disable interrupts while an interrupt is being processed or use a priority scheme.

Symmetric Multiprocessors (SMP)

Two compatible processors, share the same main memory connected by a bus, share access to I/O devices, controlled by an integrated OS that allows processors to interact.

How are multiple interrupts dealt with?

Using priority for each interrupt or disabling interrupt handling while another interrupt is active.

Scaling (SMP)

Vendors can offer a range of products with different price and performance characteristics.

Main Memory

Volatile, contents are lost when computer is shut down, referred to as real memory or primary memory.

Interrupt-Driven I/O

Wait for interrupt from the I/O module, processor executes required data transfers, functions and the resumes processing. More efficient that programmed but requires interruption of processor.

Program

A set of instructions stored in memory.

What is an interrupt?

A mechanism provided by the processor to interrupt the normal sequencing of the processor. This allows the processor to handle I/O, errors, etc.

Performance (SMP)

A system with multiple processor will yield greater performance if work can be done in parallel.

Secondary Memory

Also referred to as auxiliary memory. External, nonvolatile, used to store program and data files.

Incremental Growth (SMP)

An additional processor can be added to enhance performance.

Execute Stage

CPU executes queued program/instruction.

Fetch Stage

CPU fetches next program/instruction. Program counter holds address of the instruction to be fetched. "PC" is incremented.

Cache Principles

Contains a copy of a portion of main memory, Processor first checks cache. If not found, a block of memory is read into the cache. Because of locality of reference, it is likely that many of the future memory references will be to other bytes in the block.

In general terms, what are the four distinct actions that a machine instruction can specify?

Control, Processor Memory, Processor I/O, Data Processing

Processor

Controls the operation of the computer, performs the data processing functions, referred to as the CPU.

What characteristics distinguish the various elements of a memory hierarchy?

Decreasing cost per bit, increasing capacity, increasing access time, decreasing frequency of access by processor.

Operating System

Exploits the hardware resources of one or more processors, provides a set of services to system users, manages secondary memory and I/O devices.

Hardware Failure

Generated by a failure, such as power failure or memory parity error.

Timer Interrupt

Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis.

I/O

Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions.

Program Interrupt

Generated by some condition that occurs as a result of an instruction execution such as: arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, and reference outside a user's allowed memory space.

The Memory Hierarchy

Going down the pyramid, decreasing cost per bit, increasing capacity, increasing access time, decreasing frequency of access to the memory by the processor.

Greater capacity of memory also...

Grants slower access speed.

Faster access time to memory.

Greater cost per bit.

I/O AR

Input/output address register

I/O BR

Input/output buffer register

IR

Instruction Register

Microprocessor

Invention that brought about desktop and handheld computing. Processor on a single chip. Fastest general purpose processor. Multiprocessors. Each chip (socket) contains multiple processors (cores).

Cache Memory

Invisible to the OS, interacts with other memory management hardware, processor must access memory at least once per instruction cycle, processor execution is limited by memory cycle time, exploit the principle of locality with a small, fast memory.

What is cache memory?

Invisible to the OS, is a copy of recently used blocks of memory from the main memory. Is designed to increase performance and reduce the time it takes for the processor to access the information it needs.

Multicore Computer

Known as chip multiprocessor, combines two ore more processors (cores) on a single piece of silicon (die).

Cache Design

Main categories are: cache size, block size, mapping function, replacement algorithm, write policy and number of cache levels.

Define the two main categories of processor registers.

Memory Address Register (MAR) and Memory Buffer Register (MBR)

MAR

Memory address register

MBR

Memory buffer register

Principle of Locality

Memory references by the processor tend to cluster. Data is organized so that the percentage of accesses to each successively lower level is substantially less than that of the level above.

I/O Modules

Moves data between the computer and external environments.

What is the difference between a multiprocessor and a multicore system?

Multiprocessors are interconnected by a bus, multicore systems are multiple processors, called cores, on the same silicon piece called a die.

Direct Memory Access

Performed by a separate module on the system bus or incorporated into an I/O module. Transfers an entire block of data directly to and from memory w/o going through the processor. More efficient than interrupt-driven or programmed I/O.

List the four main elements of a computer.

Processor, I/O Module, Main Memory, System Bus

PC

Program Counter

Interrupts

Provided to improve processor utilization, stops the normal sequencing of the processor. Used when processor has to pause to wait for I/O device.

System Bus

Provides for communication among processors, main memory, and I/O modules.

How are temporal and spatial locality exploited?

Recently used instructions and data values kept in cache for temporal, Prefetching and large caches for exploiting spatial.

Greater capacity of memory.

Smaller cost per bit.

What is the difference between spatial locality and temporal locality?

Temporal locality refers to the tendency for a processor to access memory that has been used recently. Spatial locality is the tendency for a processor to access memory because it behaves sequentially and clusters.

Availability (SMP)

The failure of a single processor does not halt the machine.

Programmed I/O

The module performs the requested action then sets the appropriate bits in the status register. The processor periodically checks the status of the modules until it determines the instruction is complete. This technique severely degrades the performance level of the entire system.