Sequential Logic

sequential logic verilog

always use ALWAYS blocks always @ (posedge CLK) -> D ff always @ (clk, d) -> d latch always blocks = behavioral verilog

reg vs wire

// reg if set in always block // wire if assigning inside not always (combinational) i.e. wire is for internal variables

D latch (transparent, level-sensitive latch)

Captures input may also have WE input, as in if WE = 1 latch is open, D = Q WE = 0, latch is closed, Q holds prev value WE can equal clock

level sensitive

Enabled by a logic HIGH or LOW level.

flip flop

bistable element with clock input, edge-triggered state of flip-flop changes only in response to a clock edge

4 bit binary counter (163)

LD, CLR = active low CLR is synchronous reset, force to 0 if CLR = 0 LD = 0 then load ABCD ENT/ENP = enable count Holds if CLR = LD = 1 and ENT/ENP = 0 has RCO, which is ripple carry out (1 if outputs QABCD are 1111 and ENT = 1) counts 0 to 15 then automatically resets to 0

up counter logic

LSB toggles every clock tick bit 2 toggles on next clock tic when rightmost bit was 1 previously bit 3 toggles on next clock tic when rightmost two bits were 1 previously (down counter is if they were 0 previously)

binary counter

N bit binary counter has clock, reset inputs, N bit output Q reset inits Q to zero counter advances thru 2^N possible outputs, incrementing on rising edge of the clock

register

N bit register is bank of N flip flops that share common CLK input single D flip flop = 1 bit register

bistable element

two stable states ex. two not gates in a cycle (if Q=0, it will stay 0, likewise if Q = 1) >> cross-coupled inverters (input of one is output of another) >> simplest latch state variable is Q --> if Q = 0 we know circuit is 0 forever, likewise for 1

if counter, think

T flip flop!! toggling!! implemented w d flip flop

types of counters

up down free running (forever, looping) divide by n (0....n-1, 0....) n to m (n....m, n....)

make compact D latch

use a transmission gate problemos: floating output node Q, and no buffers may cause malfunctions if there are noise spikes

enabled flip flop (i.e. D flip flop with load)

When EN is true, the enable flip flop acts like reg D flip flop i.e. when on edge, L = 1, D -> Q on edge and L = 0, Q same if clock = 1, 0, Q same When EN is false, enabled flip flop retains its state ways to build: multiplexer with ENABLE select (built with D flip flop and 2 to 1 mux, load is selector for mux) CLK AND EN to determine clk signal (not preferred, performing logic on clock is bad idea)

if clk, think sequential

always block w <=

use 163 to make free running up counter

always enabled increments every clock tick, VDD To CLK/LD/ENT/ENP

D flip flop

can be built from two back to back D latches controlled by complementary clocks D flip flop copies D to Q on the rising edge of clock, and remembers its state at all other times CAPTURE D ON TRIG EDGE OF CLOCK (rising = + edge triggered, falling = - edge triggered) >> unlike latch which changes whenever clock input changes regardless of edge symbol: D, clock with triangle, Q and Q bar

194 shift register

can shift right Rin -> A-> B -> C (lose D) can shift left LIN -> D-> C-> B (lose A) LIN always shifted innnnnnn Load S1=S0 = 1 Hold S1 = S0 = 0 S1=1, S0=0 shift left wraparound isnt built in

shift register

clock, serial input Sin, serial output Sout and N parallel outputs Q N-1 : 0 on each rising edge of clock, new bit shifted in from Sin, all contents shifted forward, last bit available at Sout After N cycles, past N inputs all available in parallel at Q can be constructed from N D flip flops (serial in, serial out)

cascading counter

counts higher bits if RCO = 1 then carry to next counter (enable counting on next one)

binary counter with hold

counts if EN = 1, pause if EN = 0

S bar R bar latch

cross coupled NAND gates S bar = 0 = R bar = invalid S bar = 1 (reset to 0) R bar = 1 (reset to 1) S bar = 1, R bar = 1 -> hold current value

sequential logic

depend on inputs and state (past history) storage elements hold state variables clock advances circuit

always_ff @ (posedge clk, posedge reset)

flip flop that is asynchronously resettable

latch

for memory

x to y counters

i.e. divide by n counters, CLR = 0 at value n-1 Load x when count reaches y

T flip flop with EN

if EN = 1, output toggles output doesn't change if EN = 0

serial in, parallel out shift register

input goes in serially output is available at all shift registers i.e. Q coming from any flip flop

clock

input to seq circuit that changes output at pre determined rate period = time between rising/falling edges of same type freq = 1/period (in Hz)

latch vs flip flop

latches outputs can change at any point if input changes whereas flip flops' outputs change at certain times only (i.e. rising edge of a clock)

4 bit ring counter using 194

load 0001 when RESET=1 shift left and wraparound, wraparound means tie QA to LIN (MSB) left shift only S1 = 1 always

elem with N stable states conveys

log 2 N bits of information (bistable elem stores one bit)

serial in, serial out shift register

n d ff series serin apeears at serout ater n clock ticks

multi bit latch

one WE that controls opening/closing latch lots of D latches that can store one bit each

enabled register

only responds to clock if ENABLED retains old value if EN = false

toggle (T) flip flop

output toggles every CLK implement with D flip flop (Q bar goes to D)

ring counter

single 1 shifts through outputs 0001 0010 0100 1000 0001

system state

state of digital sequential circuit is a set of bits called state variables containing all info ab past necessary to explain future behavior

transmission gates

two "openers", where top one is positive-driven and bottom one is negative-driven so if both are correctly driven, D input --> Q output otherwise, D does not pass through

SR latch

two cross coupled NOR gates with inputs S and R and outputs Q and Q bar S = set (when 1, Q set to 1, Q bar is opp) R = reset (when 1, Q reset to 0, Q bar to 1) when neither S or R is asserted, Q remembers its old value if you set and reset at the same time, circuit outputs = 0 (but invalid!) state variable = Q symbol: square with R, S, Q, Q bar

shift register with parallel load

when LOAD is asserted, flip flops loaded in parallel from D inputs otherwise, shift register shifts normally (parallel to serial converter)

resettable/settable flip flop (register)

when RESET is false, acts like ordinary D flip flop when RESET is true, flip flop ignores D and resets to output 0 can be synchronous (reset on rising edge of CLK) or async (reset independent of CLK, whenever RESET or SET = true) **there also exist settable flip flops which load a 1--> if set = 1, Q = 1 can have flip flop that is both SET and RESET