Chapter 6.3

MIMD

Multiple Instruction streams, Multiple Data streams. A multiprocessor.

MISD (example)

No Current Examples

vectors

* using pipelined executions units * stream data from/to vector registers to units * significantly reduces instruction-fetch bandwith

Single Instruction, Single Data

Only one instruction stream is being acted on and only one data stream is being used. Deterministic.

data level parallelism

Parallelism achieved by performing the same operation on independent data.

philosophy of vector architecture

Collect data elements from memory, put them in order into a large set of registers, operate on them sequentially in registers using pipelined execution units, and then write the results back to memory.

Flynn's Taxonomy

Distinguishes multi-processor computer architectures according to how they can be classified along the two independent dimensions of Instruction and Data.

MIMD (example)

Intel Core i7

SISD (example)

Intel Pentium 4

SIMD (example)

SSE Instructions of x86

SIMD

Single Instruction stream, Multiple Data streams. The same instruction is applied to many data streams, as in a vector processor.

SISD

Single Instruction stream, Single Data stream. A uniprocessor.

SPMD

Single Program, Multiple Data streams. e conventional MIMD programming model, where a single program runs across all processors.

Single instruction, Multiple data

Single instruction, all processing units execute the same instruction. Multiple data, each processing unit can operate on a different data element. Best suited for specialized problems with high degree of regularity, image processing with synchronous and deterministic action.

vector arhictecture

The a set of vector registers. Thus, a vector architecture might have 32 vector registers, each with 64 64-bit elements.