Chapter 7 - Operand Addressing And Instruction Representation

For example, an operand that specifies indirection through register 6 causes a processor to perform two steps:

- Obtain A, the current value from register 6. - Interpret A as a memory address, and fetch the operand from memory.

Although it works well for arithmetic or logical operations, a 1-address design does not allow instructions to specify two values.

A 1-address design requires two instructions that load the value into the accumulator and then store the value in the new location. The design is especially inefficient for a system that moves graphics objects in display memory.

An immediate value is the least expensive because the value is located in the instruction register (i.e.,in the instruction itself).

A general-purpose register reference is slightly more expensive than an immediate value.

Operand used as a source (item used in the operation) - A signed constant in the instruction - An unsigned constant in the instruction - The contents of a general-purpose register - The contents of a memory location Operand used as a destination (location to hold the result) - A general-purpose register - A contiguous pair of general-purpose registers - A memory location

A source operand specifies a value and a destination operand specifies a location.

Larger Range Of Immediate Values.

A string of k bits can hold 2^k possible values. Thus, the number of bits allocated to an operand determines the numeric range of immediate values that can be specified. Increasing the range of immediate values results in larger instructions.

If the processor uses many types of operands, the set of opcodes can be extremely large.

As an alternative, an explicit operand encoding associates type information with each operand.

7.9 Explicit And Implicit Operand Encoding

The instruction contains a bit field for each operand, but an architect must specify exactly what the bits mean (e.g., whether they contain an immediate value, the number of a register, or a memory address). Computer architects have used two interpretations of operands: implicit and explicit.

A processor usually contains a special internal register, called an instruction register, that is used to hold an instruction while the instruction is being decoded.

The possible types of operand addresses and the cost of each can be envisioned by considering the location of the operand and the references needed to fetch the value.

†Some architects reserve the term 2-address for instructions in which both operands specify a memory location, and use the term 1 1/2- address for situations where one operand is in memory and the other operand is in a register.

‡To increase performance, modern 3-address architectures often limit operands so that at most one of the operands in a given instruction refers to a location in memory; the other two operands must specify registers.

In such cases, a processor performs the following steps:

- Obtain M, the value in the operand itself. - Interpret M as a memory address, and fetch the value A from memory. - Interpret A as another memory address, and fetch the operand from memory.

7.12 Values In Memory And Indirect Reference

Accessing a value in memory is significantly more expensive than accessing a value in a register. Although it may make programming easier, a design in which each instruction references memory usually results in lower performance. Thus, programmers usually structure code to keep values that will be used often in registers and only reference memory when needed.

As the figure indicates, most architectures allow an operand to be a constant.

Although the operand field is small, having an explicit constant is important because programs use small constants frequently (e.g., to increment a loop index by 1); encoding a constant in the instruction is faster and requires fewer registers.

7.3 Zero Operands Per Instruction

An architecture in which instructions have no operands is known as a 0-address architecture. How can an architecture allow instructions that do not specify any operands? The answer is that operands must be implicit. That is, the location of the operands is already known. A 0-address architecture is also called a stack architecture because operands are kept on a run-time stack.

7.9.1 Implicit Operand Encoding

An implicit operand encoding is easiest to understand: the opcode specifies the types of operands. That is, a processor that uses implicit encoding contains multiple opcodes for a given operation — each opcode corresponds to one possible combination of operands. Figure 7.3 An example of addition instructions for a 2-address processor that uses implicit operand encoding. A separate opcode is used for each possible combination of operands.

When we discuss memory, we will see that allowing an operand to specify a register plus an offset is especially useful when referencing a data aggregate such as a

C language struct because a pointer to the structure can be left in a register and offsets used to reference individual items.

Ease Of Programming.

Complex forms of operands make programming easier. For example, we said that allowing an operand to specify a register plus an offset makes data aggregate references straightforward. Similarly, a 3-address approach that provides an explicit target means a programmer does not need to code separate instructions to copy results into their final destination.

Decreased Hardware Size And Complexity.

Decoding complex forms of operands requires more hardware than decoding simpler forms. Thus, limiting the types and complexity of operands reduces the size of the circuitry required. Of course, the choice represents a tradeoff: programs are larger.

Thus, in the example instruction set, an add instruction requires three operands: two that specify values to be added and a third that specifies a location for the result.

Despite the intuitive appeal of a processor in which each instruction can have an arbitrary number of operands, many processors do not permit such a scheme. To understand why, we must consider the underlying hardware. First, because an arbitrary number of operands implies variable-length instructions, fetching and decoding instructions is less efficient than using fixed-length instructions. Second, because fetching an arbitrary number of operands takes time, the processor will run slower than a processor with a fixed number of operands.

Examples of operands on an architecture that uses explicit encoding.

Each operand specifies a type as well as a value.

7.11 Tradeoffs In The Choice Of Operands

Ease Of Programming., Fewer Instructions., Smaller Instruction Size., Larger Range Of Immediate Values., Faster Operand Fetch And Decode., Decreased Hardware Size And Complexity. The answer is simple: each style represents a tradeoff between ease of programming, size of the code, speed of processing, and complexity of the hardware.

A reference to memory is more expensive than a reference to a register.

Finally, double indirection, which requires two memory references, is the most expensive.

Some of the instructions in a stack computer allow a programmer to specify an operand.

For example, most zero-address architectures include a push instruction that inserts a new value on the top of the stack, and a pop instruction removes the top value from the stack and places the value in memory.

We know that an instruction has a bit field for each operand, but questions arise about how the bits are interpreted.

How is each type of operand represented in an instruction? Do all operands use the same representation? What semantic meaning is given to a representation?

We said that an instruction is usually stored as an opcode followed by zero or more operands.

How many operands are needed? The discussion in Chapter 5 assumes that the number of operands is determined by the operation being performed. Thus, an add instruction needs at least two operands because addition involves at least two quantities.

One extreme form of operand involves double indirection, or indirection through a memory location.

However, instead of loading or storing a value to address M, the processor assumes M contains the memory address of the value.

Similarly, a Boolean not instruction needs one operand because logical inversion only involves one quantity.

However, the example MIPS instruction set in Chapter 5 employs an additional operand on each instruction that specifies the location for the result.

Double indirection that goes through one memory location to another can be useful when a program has to follow a linked list in memory.

However, the overhead is extremely high (execution of a single instruction entails multiple memory references).

However, parallel hardware uses more space on a chip and requires additional power.

In addition, the number of pins on a chip limits the amount of data from outside the chip that can be accessed in parallel. Thus, parallel hardware is not an attractive option in many cases (e.g., a processor in a portable phone that operates on battery power). Some processors limit instructions to three operands.

An architecture that limits each instruction to a single operand is classified as a 1-address design.

In essence, a 1-address design relies on an implicit operand for each instruction: a special register known as an accumulator†.

The chief disadvantage of implicit encoding is apparent from Figure 7.3: multiple opcodes are needed for a given operation.

In fact, a separate opcode is needed for each combination of operands.

Illustration of the hardware units accessed when fetching an operand in various addressing modes. Indirect references take longer than direct references.

In the figure, modes 3 and 5 each require the instruction to contain a memory address.

Fewer Instructions.

Increasing the expressive power of operands reduces the number of instructions in a program. For example, allowing an operand to specify both a register and an offset means that the program does not need to use an extra instruction to add an offset to a register. Increasing the number of addresses per instruction also lowers the count of instructions (e.g., a 3-address processor requires fewer instructions than a 2-address processor). Unfortunately, fewer instructions produce a tradeoff in which each instruction is larger.

7.6 Three Operands Per Instruction

Instead, the point is that the third operand can specify a destination.

Faster Operand Fetch And Decode.

Limiting the number of operands and the possible types of each operand allows hardware to operate faster. To maximize speed, for example, an architect avoids register-offset designs because hardware can fetch an operand from a register much faster than it can compute the value from a register plus an offset.

Smaller Instruction Size.

Limiting the number of operands, the set of operands types, or the maximum size of an operand keeps each instruction small because fewer bits are needed to identify the operand type or represent an operand value. In particular, an operand that specifies only a register will be smaller than an operand that specifies a register and an offset. As a result, some of the smallest, least powerful processors limit operands to registers — except for load and store operations, each value used in a program must come from a register. Unfortunately, making each instruction smaller decreases the expressive power, and therefore increases the number of instructions needed.

The point is:

No single form is optimal for all processors because the choice represents a compromise among functionality, program size, complexity of the hardware required to fetch values, performance, and ease of programming.

The point is:

On a computer that follows the Von Neumann Architecture, the time spent accessing memory can limit the overall performance. Architects use the term Von Neumann bottleneck to characterize the situation, and avoid the bottleneck by choosing designs in which operands are found in registers.

One operand is in the instruction and the processor uses the value of the accumulator as a second operand.

Once the operation has been performed, the processor places the result back in the accumulator.

Recall that conventional computers that store both programs and data in memory are classified as following a Von Neumann Architecture.

Operand addressing exposes the central weakness of a Von Neumann Architecture: memory access can become a bottleneck. That is, because instructions are stored in memory, a processor must make at least one memory reference per instruction.

We use the term immediate value to refer to an operand that is a constant.

Some architectures interpret immediate values as signed, some interpret them as unsigned, and others allow a programmer to specify whether the value is signed or unsigned.

The discussion above implies that each operand consists of a single value extracted from a register, memory, or the instruction itself.

Some processors do indeed restrict each operand to a single value. However, other processors provide hardware that can compute an operand value by extracting and combining values from multiple sources. Typically, the hardware computes a sum of several values.

If one or more operands specify items in memory, the processor must make additional memory references to fetch or store values.

To optimize performance and avoid the bottleneck, operands must be taken from registers instead of memory.

One approach is known as a register-offset mechanism. The idea is straightforward: instead of two subfields that specify a type and value, each operand consists of three fields that specify a register-offset type, a register, and an offset.

When it fetches an operand, the processor adds the contents of the offset field to the contents of the specified register to obtain a value that is then used as the operand.

To overcome the limitations of 1-address systems, designers invented processors that allow each instruction to have two addresses.

With a 2-address processor, an operation can be applied to a specified value instead of merely to the accumulator.

Of course, the instruction set for a 1-address processor includes instructions that allow a programmer to

load a constant or the value from a memory location into the accumulator or store the current value of the accumulator into a memory location.

Because it allows an instruction to specify two operands, a 2-address processor can

offer data movement instructions that treat the operands as a source and destination. For example, a 2-address instruction can copy data directly from location Q to location R†: move Q R