CS270 Midterm 2 (LC3)
Which phase happens first, DECODE or FETCH OPERANDS
DECODE
What is NOT a benefit of using a stack for memory management?
Data related to one function can be accessed by another function by altering the Frame pointer offset
Which is not stored on the stack?
Dynamic allocations
Which phase happens first, EVALUATE ADDRESS or EXECUTE?
EVALUATE ADDRESS
Control Instructions change the value of PC in the __________ phase
Execute
When used in the Linux terminal/shell the & character has what effect?
Executes the command in the background so the shell does not have to wait to continue executing commands
A single assembly language name for an opcode can be translated into two machine language codes. (T/F)
F
An I/O device can signal the microprocessor when it needs to interact with it. This form of interaction is known as polling. (T/F)
F
Bits [11:0] of the RET instruction specify the address to return to. (T/F)
F
In LC-3 ISA, only BRx, JMP, JSR/JSRR, RET, and RTI instructions modify the value of the Program Counter. (T/F)
F
In structured programming, one must enter a processing box at exactly one entrance point, but can leave the processing box at up to 4 exit points, depending on the nature of the processing being performed. (T/F)
F
The EXECUTE phase of the instruction cycle is accompanied by a test for the interrupt signal. (T/F)
F
The Evaluate Address phase can happen before the instruction Decode phase. (T/F)
F
The declaration of a variable as a struct is one of the constructs of structured programming. (T/F)
F
When using a stack to implement storage for function parameters and local variables, the number of function parameters cannot exceed 3. (T/F)
F
Accessing a value in a register is slower than accessing a value in memory.
False
According to the LC-3 datapath, the following register transfers could occur in the same clock cycle: IR⟵PC MAR⟵Reg[3]+Reg[5]
False
All LC-3 instructions modify the condition codes.
False
During the setup for an interrupt the Program Status Register (PSR) is pushed onto the supervisor stack so that when the interrupt routine is complete the RTI instruction can set the Program Counter to the address of the instruction that was about to execute before the interrupt occured.
False
For an LC-3 instruction that uses the PC-Relative addressing mode, bits [15:9] of the address of the operand are the same as bits [15:9] of the address of the instruction.
False
In one clock cycle it is not possible to have multiple registers receive data.
False
In structured programming, one must enter a processing box at exactly one entrance point, but can leave the processing box at up to 4 exit points, depending on the nature of the processing being performed.
False
In the LC-3, when a key on the keyboard is pressed, KBDR holds the 2's complement representation of that key.
False
Memory operations take one cycle to complete just like other operations in the LC3 instruction cycle.
False
Some symbol table entries are created in the second pass of a two-pass assembler.
False
Sometimes it is possible to carry out only a part of instruction, in which case, the computer only carries out that part of the instruction that it can.
False
The .end pseudo-op is translated into the halt opcode. It stops execution of the program.
False
The EXECUTE phase of the instruction cycle is accompanied by a test for the interrupt signal.
False
The Evaluate Address phase can happen before the instruction Decode phase.
False
The LC-3 uses special input/output instructions to communicate with I/O devices.
False
The NOT instruction does not require cycle 2 of the Fetch phase of the instruction cycle.
False
The TRAP instruction stores the address of the instruction following the TRAP instruction in R0 before loading the PC with the starting address of the service routine.
False
The Trap routine PUTS, which writes a null terminated string of characters to the display, expects R0 to contain a value corresponding to the ASCII value of the first character to be displayed. This value will then be incremented to create the address of the next character.
False
The following is valid for the left hand side of a RTN transfer: Reg[src] + Reg[dst]
False
The function of the Instruction Register is to point to next instruction to be processed.
False
The stack is only useful for implementing functions the use recursion.
False
When using a stack to implement storage for function parameters and local variables, the number of function parameters cannot exceed 3.
False
When using the stack protocol all functions must take at least one parameter/argument.
False
The PC is incremented so that during the next instruction cycle, the next instruction will be processed. This happens during the ____________ phase.
Fetch
The assembler will recognize TRAP x20 as the following string as well:
GETC (read sincle character, no echo)
What does the -tk in lc3sim-tk signify?
Graphical version of simulator
The assembler will recognize TRAP x25 as the following string as well:
HALT (Halt program)
The assembler will recognize TRAP x23 as the following string as well:
IN (Print prompt to console, read and echo character ffrom keyboard)
The FETCH phase loads the next instruction into which register?
IR
To store the instruction that is currently being executed, the control unit has an ____ (Two letter register abbreviation)
IR
x86, ARM, RISKV, and MIPS are all examples of a(n)?
ISA
The following LC-3 instruction is located at memory address 0x5F55. Which of the following describes the operation of this instruction? 0x04FF
If the zero condition code is set, the instruction will load 0x6055 into the PC.
How does the RTI instruction know if it needs to switch from the supervisor stack to the user stack?
It checks if the privilege level of the PSR it pops off the supervisor stack is 1
What does this instruction do?0000 1110 0000 0000
It is a branch instruction that is always taken, but since the PC offset is 0 results in no change to the PC.
What does this instruction do? LEA R5, LAB
It loads into R5 the address of the location with label LAB
What does this instruction do? STR R1, R2, #0
It stores the contents of R1 into a memory location, the address of this location is in R2.
In a program, you have not yet placed a value in register R5? What do you think it contains?
Its contents are undefined until you put a value in it. The value in it may depend on factors you may not know about.
What are the differences between the JMP and BR instructions?
JMP - unconditional branch; PC is found in source register BR - conditional branch; PC is set to PC + offset
Which of the following instructions can cause the control flow to jump ANYWHERE in memory?
JSRR
What instruction(s) accomplish the following: Add contents of memory location LOC1 to contents of R1, and leave result in R1. i.e. R1 <- R1 + MEM[LOC1]
LD R2, LOC1 ADD R1, R2, R1
What instruction would you use to move a value in a memory location labeled Val to register R4?
LDR R4, Val
Which of the following instructions take more than four cycles to execute?
LDR, LDI, TRAP, ST
Which of the following LC-3 instructions does not access memory to fetch its operand?
LEA
What instructions would achieve the same result as the LDI instruction? .ORIG x3000 MAIN ADD R2, R2, #3 LDI R2, FAR FAR .FILL xFFFC
LEA R2, FAR LDR R2, R2, #0
In LC3, the Pop operation for a stack is implemented by doing this:
Loading data into a register from the top of the stack and then incrementing the stack pointer.
To read the contents of a memory location, we first place the address of that location in the _______ (Three letters)
MAR
Identify the transfers that take place as part of every instruction.
MAR <- PC IR <- MDR PC <- PC + 1 MDR <- Mem[MAR]
In the FETCH phase, an instruction is transferred from ______ to the Instruction Register.
Memory
To implement Memory Mapped IO, extra hardware will be needed in the
Memory Controller
If we were trying to add IO capabilities to a processor and memory system that did not have any IO functionality, and we could not add to / change the processor hardware (components on the inside of the LC3's bus), what type of IO would we have to implement?
Memory Mapped IO
Which of the following LC-3 instructions can only have operands that are in registers (i.e. cannot have immediate or memory operands)?
NOT
How can an OR instruction be simulated on the LC3?
NOT R1, R1 NOT R2, R2 AND R3, R1, R2 NOT R3, R3 (DeMorgan's Law)
You want to perform bit-wise logical OR of the contents of R1 and R2 and place the result in R3. Which code will do that?
NOT R1, R1 NOT R2, R2 AND R3, R1, R2 NOT R3, R3
The assembler will recognize TRAP x21 as the following string as well:
OUT (output character to console)
What offsets from the Frame Pointer (R5) will be affected if the function that the stack frame belongs to does not have a return value, i.e. returns void (This means that space for the return value is not allocated in the stack frame).
Offset to the functions parameters
According to the lecture slides, when an interrupt happens in the LC3, what registers are pushed onto the supervisor stack to save the state of the currently executing program?
PSR (containing P, PL and N,Z,P fields) and PC
The assembler will recognize TRAP x22 as the following string as well:
PUTS (Write string to console)
What does the code do? ADD R6, R6, #-1 STR R5, R6, #0 ... LDR R5, R6, #0 ADD R6, R6, #1
Pushes and pops the frame pointer
On completion of the standard LC-3 input service routine, register _______ contains the ASCII code of the character typed in.
R0
The instruction 0011 0001 0010 1111 at memory location 0x5611 stores the value of register ___ into memory location 0x____ when executed.
R0 0x5541
What is the OUT Trap expecting when it is called?
R0 to have a characters ASCII value
The instruction 0011 0001 0010 1111 at memory location 0x5611 stores the value of register [ Select ] into memory location when executed.
R0; 0x5541
The test for an interrupt signal is done after which phase of the instruction cycle?
STORE RESULT
Which of the following instructions can reference a memory location that is #1000 locations from the instruction? LEA ADD LD STR All of the above None of the above
STR
Write an instruction that will do the followingmem[R1+3] <- R2i.e. copies contents of R2 into a memory location with address given by contents of R1 plus 3.
STR R2, R1, #3
.BLKW 3 means what?
Set aside 3 sequential memory locations.
A device register holds either the data being transferred between the I/O device and the computer, or information about the I/O device. (T/F)
T
A stack where the stack pointer is updated with every operation is more efficient than a stack where the data moves after each operation since the cost of changing the contents of the stack pointer is much less than the cost of moving all the data. (T/F)
T
Changing R7 without saving its contents during a service routine is problematic as it destroys the linkage back to the initiating program.(T/F)
T
For the LC-3 ISA, the ADD instruction does not require an EVALUATE ADDRESS phase. (T/F)
T
If R6 is the stack pointer and each element in the stack occupies two memory locations, a push operation on the stack requires that R6 be decremented by 2. (T/F)
T
If bit 15 in the DSR is set to 1, the microprocessor can transfer an ASCII code to display on the monitor. (T/F)
T
If the I/O service routine writing to the monitor does not check DSR before writing to DDR, some characters may not be displayed on the monitor. (T/F)
T
If the keyboard hardware does not check the KBSR before writing to the KBDR, the processor might miss some characters that were typed. (T/F)
T
In the LC-3, the operating system uses the RET instruction to return control to the user program. (T/F)
T
One way to stop execution of a program during debugging is by setting one or more breakpoints. (T/F)
T
The .blkw pseudo-op sets aside some number of memory locations in the program space, probably to be used later for storing values. (T/F)
T
The LC-3 has two device registers to handle input from the keyboard. The keyboard data register (KBDR) and the keyboard status register (KBSR). (T/F)
T
The Location Counter is a device that is used to translate an assembly language program but not used to execute that program. (T/F)
T
What does the PC register contain after the FETCH phase?
The memory address of the next instruction
Interrupt-driven I/O is more efficient that polling because:
The processor can perform other tasks instead of constantly being in a loop checking to see if the status bit has changed.
A processor can either be in the "user" mode or the "supervisor" mode. When an interrupt occurs,
The processor will be in the supervisor mode while the interrupt service routine is being executed.
If the input service routine reads KBDR without checking the ready bit of KBSR, the following can happen:
The program could read the same key multiple times.
R6 is the stack pointer. What are the contents of R0 after this operation:
The value of the top of the stack
What is the purpose of the LD.* control signals in the LC-3 datapath (e.g., LD.PC, LD.MAR, etc.)?
To enable a register for writing
Why do we need the JSRR instruction?
To load the PC with a value greater than 1024 locations away
On execution of this program, the user inputs two numbers. Why do we need to add the value ASCII (xFFD0) to the numbers before adding them?
To strip off the ascii template, we need to add xFFD0 which is the negative of x0030 (ascii code for 0)
A device register holds either the data being transferred between the I/O device and the computer, or information about the I/O device.
True
A stack where the stack pointer is updated with every operation is more efficient than a stack where the data moves after each operation since the cost of changing the contents of the stack pointer is much less than the cost of moving all the data.
True
According to the LC-3 datapath, the following register transfers could occur in the same clock cycle: IR⟵PC 𝐶𝐶⟵𝑆𝑖𝑔𝑛(𝑃𝐶)
True
According to the LC-3 datapath, the following register transfers could occur in the same clock cycle: PC⟵Reg[0] MAR⟵Reg[0]&Reg[1]
True
Changing R7 without saving its contents during a service routine is problematic as it destroys the linkage back to the initiating program.
True
Combination and sequential (storage) elements are components of the Data Path of a processor.
True
During the instruction cycles of an ST instruction, the MDR is written into at least twice.
True
For the LC-3 ISA, the ADD instruction does not require an EVALUATE ADDRESS phase.
True
If R6 is the stack pointer and each element in the stack occupies two memory locations, a push operation on the stack requires that R6 be decremented by 2.
True
If the I/O service routine writing to the monitor does not check DSR before writing to DDR, some characters may not be displayed on the monitor.
True
If the keyboard hardware does not check the KBSR before writing to the KBDR, the processor might read some characters that were typed twice.
True
In the LC-3, the after completing a service routine the operating system uses the RET instruction to return control to the user program.
True
In the LC-3, the user program invokes the OS to perform an I/O operation using the TRAP command.
True
The .blkw pseudo-op sets aside some number of memory locations in the program space, probably to be used later for storing values.
True
The LC-3 has two device registers to handle input from the keyboard. The keyboard data register (KBDR) and the keyboard status register (KBSR).
True
The Location Counter is a device that is used to translate an assembly language program but not used to execute that program.
True
The controller part of a processor can be implemented with combinational logic or a control store.
True
The instruction 0xEE00 at memory location 0xF011 sets the N condition code when executed in the LC3 simulator we are using.
True
The return address at a recursive function call (e.g., when Fibonacci calls Fibonacci) is always the same.
True
The stack pointer keeps track of the first element to be popped off the stack.
True
We can evaluate any arithmetic expression using the run-time stack.
True
A function X calls function Y, using the activation record format used in our text. It involves, among other things, a sequence of PUSHes and POPs. The sequence is:
X: Pushes arguments. Beginning of Y: Pushes R7, R5. End of Y: Pops local variables, R5, R7. X: Pops return value, arguments
In the DDR, bits ______ are used to transfer data from the processor to the monitor.
[7:0]
A semicolon (;) alone on a line is
a comment that serves to make the program more readable to a human by separating two parts of the program with a blank line
The Program Counter (PC) contains the
address of the next instruction to be processed
When would you use .BLKW? .FILL?
allocate a block of memory (value is unknown); store inside memory address, value is known
An LC-3 instruction ADD R1,R2, #45 produces an error. It will be caught at ______ time.
assembly
Each phase of an instruction cycle requires
between 0 and some finite value n cycles to do its job.
The term ___________ denotes the case where the called program saves the contents of registers whose contents will be changed during the invocation of the called program.
callee save
The LC-3 ADD instruction:
can add a 16-bit value to a sign-extended 5-bit value
The ____________ construct is appropriate when one of two tasks is to be performed, depending on the state of some variable.
conditional
The finite state machine that controls all of the activity in a computer is in what part of the computer?
control unit
Once inside the LC3 command line simulator what should you enter to run the file br.obj
file br.obj
The clock _________ is the __________ of the clock __________
frequency, inverse, period
If the operand of an instruction is a part of the instruction, the operand is called a(n) ___________operand.
immediate
Which two addressing modes do operate instructions such as ADD, AND, and NOT use?
immediate and register
Where does the ADD instruction fetch its operands from? (multiple answers may apply)
immediate value (operand encoded in the instruction), and registers
An important first step in any algorithm, or computer program, is to _________ all the variables, that is, to put each variable into a known state.
initialize
An important first step in any algorithm, or computer program, is to ___________ all the variables, that is, to put each variable into a known state.
initialize
A gas pedal is to a car what a(n) instruction is to a(n) ISA
instruction; ISA
The constructs of structured programming are
iterative conditional sequential
A __________ is a collection of programs/functions that can be used by application programmers to perform frequent tasks.
library
If one module contains the pseudo-op .EXTERNAL A, and no module contains the label A, the error will be detected at
link time
If memory accesses take 100 times more than register accesses, then a LDR instruction will take ___ machine cycles than an JMP R3 instruction . fewer more same number of
more
The following example reads in a character from the keyboard. Is it interrupt driven I/O or polling? START LDI R1, A BRzp START LDI R0, B BR FOO ;go somewhere else once done A .FILL xFE00 ;address of KBSR B .FILL xFE02 ;address of KBDR
pollling
A ____________ is a message to the Assembler that helps in the translation process, but does not result in an executable instruction.
pseudo-operation
In the LC3 command line simulator to set the value of a register R1 to the value xFF03 you should use what command?
register R1 xFF03
PC, IR, MAR, and MDR are ...
registers
Instructions in a program are processed ___________ unless directed otherwise by a ______________ instruction.
sequentially; Control
What is this instruction doing? STR R1, R0, #0
storing the value of R1 in the address in R2 with no offset
The instruction TRAP x25 causes the PC to be loaded with the memory address:
the contents of x0025
In LC-3 Assembly Language, the symbol #101 represents
the decimal value one hundred and one
For the assembler to process the instruction LD R5, Foo (multiple answers may apply)
the location labeled Foo can appear anywhere in the assembly file for the program the location labeled Foo may not appear in the program provided there is a pseudo-op .EXTERNAL Foo in the program
When would you use .STRINGZ? What is the last character produced by the assembler?
to create a null terminated array of characters; '\0'
Fill in the blanks:A trap instruction finds the address of the trap service routine from the System Control Block using the [ Select ] , whereas JSR obtains the address of the subroutine using the [ Select] in the instruction.
trap vector; pc offset
In the following program, what would the contents of R0 and R6 right before HALT? ;Calling program .ORIG x3000 LD R6, SPINT LD R0, A JSR Push LD R0, B JSR Push JSR Pop LD R0, C JSR Push JSR Pop JSR Pop HALT ; ;Subroutine Pop LDR R0, R6, #0 ; The actual "pop." ADD R6, R6, #1 ; Adjust stack pointer BRnzp exit ; Push ADD R6, R6, #-1 ; Adjust stack pointer STR R0, R6, #0 ; The actual "push" exit RET ; SPINT .FILL x301b A .FILL x03 B .FILL x04 C .Fill x05 .END
x0003 in R0 and x301B in R6.
What does the PC contain on executing JSR FOO in the following code fragment: .ORIG x3000 JSR FOO ADD R0,R4,R2 FOO ADD R0,R0,#1 RET
x3002
What is the value in R0 and R1 after the code executes from Main label? Array .FILL x1133 .FILL x2244 .FILL x3355 Main NOT R1, R1 LEA R2, Array LDR R0, R2, 2 LDR R1, R2, 3 HALT
x3355, x927F
The execution of the JSR instruction at location x4202, causes R7 to be loaded with:
x4203
What location will the stack pointer point to after this code executes? .ORIG x3000 Start JSR Main Main LD R6 Stack LD R3, Start PUSH R1 ADD R6, R6, #-2 PUSH R3 POP R6 Stack .FILL x4800
x4801
If R3 contains x5000 and the JSRR instruction is stored in x4000, the value of the PC after execution of JSRR R3 is:
x5000
The largest memory address that can be referenced by an LD instruction at location 0x6631 is:
x6731
To assemble a file called hello.asm from a CS department computer what command should you use?
~cs270/lc3tools/lc3as hello.asm
In the LC-3, what must the value of the MEM.RW signal be if you wanted to perform a memory read operation?
0
What value is in R5 after the code? DATA .FILL 0x1234 LD R5, DATA AND R5, R5, #15 NOT R5, R5
0xFFFB
In the LC-3, what must the value of the MEM.EN signal be if you wanted to perform a memory write operation?
1
In the LC-3, what must the value of the MEM.RW signal be if you wanted to perform a memory write operation?
1
An instruction requires a LABEL if 1. it is the target of a branch 2. it is the symbolic address of a data element that is referenced
1, 2
Which of the following instructions move the value in R5 into R6? 1. 0001 1101 0110 0000 2. 0101 1101 0111 1111 3. 1001 1101 0111 1111
1, 2
After the execution of which of the following instructions will the value in the Program Counter (PC) be 0x306E? 1. 0000 1110 0101 1100 at location 0x3011 2. 1001 0000 0110 1110 at location 0x3064 3. 1010 0110 0110 1110 at location 0x306d
1, 3
What are the 10 steps of the stack protocol?
1. Caller pushed arguments (last to first) 2. Caller invokes subroutine (JSR) 3. Callee allocates return value, pushes R7 and R5 4. Callee sets up new R5; allocates space for local variables 5. Callee executes function code 6. Callee stores result into return value slot 7. Callee pops local vars, pops R5, pops R7 8. Callee returns (JMP R7) 9. Caller loads return value and pops argument 10. Caller resumes computation
Show two ways to set the value in the register R2 to 32
1. Label .FILL #32 LD R2, Label 2. .ZERO R2 ADD R2, R2, #8 ADD R2, R2, R2 ADD R2, R2, R2
If a processor has a frequency of 2x10^6 cycles per second what is the clock period?
1/(2x10^6) seconds
In a 16-bit address space A[15:0], if A[15:10] = 111111, were allocated to I/O device registers (i.e. most significant 6 bits of all addresses related to I/0 are 111111) The number of memory mapped I/O addresses is:
1024
Bit _____ of the Jump to Subroutine instruction specifies which addressing mode to use to determine the target address
11
Bit _____ of the Jump to Subroutine(JSR) instruction specifies which addressing mode to use to determine the target address
11
The interrupt enable bit in the KBSR and the DSR is at what bit position?
14
In KBSR, bit [ Select ] is the interrupt enable bit. If the bit is [ Select ], then interrupt-driven I/O is enabled.
14; set
In the case of the LC-3 DSR, the ready bit is:
15
What is largest positive value we can represent using LC-3 ADD instruction with immediate addressing?
15
How many bits are in the IR?
16
A key element of systematic decomposition is that the number of entrances into a processing box is exactly ______ and the number of exits out of a processing box is exactly ________ .
1; 1
The LD instruction requires _____ explicit operands.
2
The only data type supported by LC-3 is ...
2's complement integers
What data types does the LC3 ISA support?
2-complement 16-bit integers
A 16-bit instruction takes the following format <OPCODE><DR><SR><IMM> where DR specifies the destination register, SR specifies the source register, and IMM is a 2's complement immediate value. If there are 27 opcodes and 16 registers, the number of bits left to specify the immediate value is?
3
The number of memory accesses performed during the processing, i.e., entire instruction cycle, of the STI instruction is?
3
LC-3 supports how many addressing modes?
5
The Von Neumann model consists of ___ parts
5
Match the term to its position in the instruction cycle: Execute Decode Evaluate Address Store Result Fetch Fetch Operands
5 2 3 6 1 4
How many states does the LC3 state machine have?
52
How many priority levels does the LC-3 processor have?
8
If an ISA has 256 opcodes, the number of bits in the instruction encoding used to specify the opcode should be at least
8
Given an empty stack and this sequence of operations performed on the stack, what is the last value popped? push 5 push 3 push 2 pop push 9 push 3 pop pop
9
The calling convention should be such that every function is caller-independent. What does that mean?
A function should be callable from any function.
A push of the value in R3 onto the run-time stack in LC-3 requires which two commands?
ADD R6, R6, #-1 STR R3, R6, #0
A function P calls a function Q which uses 3 local variables. At the beginning of Q, the following code is needed:
ADD R6, R6, #-1; space for return value ADD R6, R6, #-1 STR R7, R6, #0; Push return address ADD R6, R6, #-1; STR R5, R6, #0; Push caller's frame pointer ADD R5, R6, #-1; Set new frame pointer ADD R6, R6, #-3; space for Q's local variables
List the addressing modes supported by the operate instructions
ADDDR and ADDI
The following transfer description in RTN does what? Reg[5] <- Reg[2] & Sext(IR[4:0])
ANDs the contents of Register 2 with the least significant 5 bits of the Instruction Register and stores the result in Register 5
An LC-3 instruction ADD R1,R2, #45 produces an error. It will be caught at
Assembly time
An LC-3 instruction ADD R6,R7,R8 produces an error. It will be caught at
Assembly time