DIGI ELECS COMPILATION 3
A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________ a) Two AND gates b) Two NAND gates c) Two NOT gates d) Two OR gates
Answer: a Explanation: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.
The characteristic equation of S-R latch is ____________ a) Q(n+1) = (S + Q(n))R' b) Q(n+1) = SR + Q(n)R c) Q(n+1) = S'R + Q(n)R d) Q(n+1) = S'R + Q'(n)R
Answer: a Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S + Q(n))R'.
A ripple counter's speed is limited by the propagation delay of _____________ a) Each flip-flop b) All flip-flops and gates c) The flip-flops only with gates d) Only circuit gates
Answer: a Explanation: A ripple counter is something that is derived by other flip-flops. It's like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.
A ripple counter's speed is limited by the propagation delay of ____________ a) Each flip-flop b) All flip-flops and gates c) The flip-flops only with gates d) Only circuit gates
Answer: a Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed of FF only and no gates are there other than FF, so only propagation delay of FF will be taken into account. Propagation delay refers to the amount of time taken in producing an output when the input is altered.
Which statement describes the BEST operation of a negative-edge-triggered D flip-flop? a) The logic level at the D input is transferred to Q on NGT of CLK b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH c) The Q output is ALWAYS identical to the D input when CLK = PGT d) The Q output is ALWAYS identical to the D input
Answer: a Explanation: By the truth table of D flip flop, we can observe that Q always depends on D. Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.
Whose operations are more faster among the following? a) Combinational circuits b) Sequential circuits c) Latches d) Flip-flops
Answer: a Explanation: Combinational circuits are often faster than sequential circuits. Since, the combinational circuits do not require memory elements whereas the sequential circuits need memory devices to perform their operations in sequence. Latches and Flip-flops come under sequential circuits.
One major difference between a NAND based S'-R' latch & a NOR based S-R latch is ____________ a) The inputs of NOR latch are 0 but 1 for NAND latch b) The inputs of NOR latch are 1 but 0 for NAND latch c) The output of NAND latch becomes set if S'=0 & R'=1 and vice versa for NOR latch d) The output of NOR latch is 1 but 0 for NAND latch
Answer: a Explanation: Due to inverted input of NAND based S'-R' latch, the inputs of NOR latch are 0 but 1 for NAND latch.
Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________ a) 00 b) 11 c) 01 d) 10
Answer: a Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So mod = 22 = 4). So after 4 clock pulses the O/P repeats i.e. 00.
For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then next state will be ___________ a) 1 b) 0 c) Don't care d) Toggle
Answer: a Explanation: For JK flip-flop to SR flip-flop, if S=1, R=0 & present state is 0 then next state will be 1 because next stage is complement of present stage.
If Q = 0, the output is said to be ___________ a) Set b) Reset c) Previous state d) Current state
Answer: a Explanation: If Q = 0, the output is said to be set and reset for Q' = 1.
For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as ___________ a) External inputs to S and R b) Internal inputs to S and R c) External inputs to combinational circuit d) Internal inputs to combinational circuit
Answer: a Explanation: If a JK Flip Flop is required, the inputs are given to the combinational circuit and the output of the combinational circuit is connected to the inputs of the actual flip flop. So, J and K will be given as external inputs to S and R. As SR flip-flop have invalid state and JK flip-flop don't.
Which of the following is correct for a gated D-type flip-flop? a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW b) The output complement follows the input when enabled c) Only one of the inputs can be HIGH at a time d) The output toggles if one of the inputs is held HIGH
Answer: a Explanation: In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is '0' then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.
In a NAND based S'-R' latch, if S'=1 & R'=1 then the state of the latch is ____________ a) No change b) Set c) Reset d) Forbidden
Answer: a Explanation: In a NAND based S'-R, latch if S'=1 & R'=1 then there is no any change in the state. It remains in its prior state. This state is used for the storage of data.
The characteristic of J-K flip-flop is similar to _____________ a) S-R flip-flop b) D flip-flop c) T flip-flop d) Gated T flip-flop
Answer: a Explanation: In an S-R flip-flop, S refers to "SET" whereas R refers to "RESET". The same behaviour is shown by J-K flip-flop.
How many flip-flops are required to construct a decade counter? a) 4 b) 8 c) 5 d) 10
Answer: a Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n. 24=16and23=8, therefore, 4 flip flops needed.
When a high is applied to the Set line of an SR latch, then ___________ a) Q output goes high b) Q' output goes high c) Q output goes low d) Both Q and Q' go high
Answer: a Explanation: S input of a SR latch is directly connected to the output Q. So, when a high is applied Q output goes high and Q' low.
The NAND latch works when both inputs are ___________ a) 1 b) 0 c) Inverted d) Don't cares
Answer: a Explanation: The NAND latch works when both inputs are 1. Since, both of the inputs are inverted in a NAND latch.
The basic latch consists of ___________ a) Two inverters b) Two comparators c) Two amplifiers d) Two adders
Answer: a Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q' = 1 and vice versa.
The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________ a) Edge-detection circuit b) NOR latch c) NAND latch d) Pulse-steering circuit
Answer: a Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the edge-detection circuit.
The output of latches will remain in set/reset untill ___________ a) The trigger pulse is given to change the state b) Any pulse given to go into previous state c) They don't get any pulse more d) The pulse is edge-triggered
Answer: a Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to change the state.
How many types of latches are ___________ a) 4 b) 3 c) 2 d) 5
Answer: a Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a modified form of SR latch whereas, T latch is an advanced form of JK latch.
How many types of sequential circuits are? a) 2 b) 3 c) 4 d) 5
Answer: a Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.
What is a trigger pulse? a) A pulse that starts a cycle of operation b) A pulse that reverses the cycle of operation c) A pulse that prevents a cycle of operation d) A pulse that enhances a cycle of operation
Answer: a Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. a) 10.24 kHz b) 5 kHz c) 30.24 kHz d) 15 kHz
Answer: b Explanation: 12 flip flops = 212 = 4096 Input Clock frequency = 20.48*106 = 20480000 Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.
Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________ a) 1 kHz b) 2 kHz c) 4 kHz d) 16 kHz
Answer: b Explanation: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:- fourth flip-flop. Since the output frequency is determined on basis of the 4th flip-flop.
A positive edge-triggered D flip-flop will store a 1 when ________ a) The D input is HIGH and the clock transitions from HIGH to LOW b) The D input is HIGH and the clock transitions from LOW to HIGH c) The D input is HIGH and the clock is LOW d) The D input is HIGH and the clock is HIGH
Answer: b Explanation: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and the clock transitions from LOW to HIGH. While a negative edge-triggered D flip-flop will store a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.
The first step of analysis procedure of SR latch is to ___________ a) label inputs b) label outputs c) label states d) label tables
Answer: b Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so because the flip flops have inverting gates inside them, hence in order to have both Q and Q complement available, we have atleast one output labelled.
How many types of the counter are there? a) 2 b) 3 c) 4 d) 5
Answer: b Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and multi-mode & (iii)modulus counter. These further can be subdivided into Ring Counter, Johnson Counter, Cascade Counter, Up/Down Counter and such like.
Which of the following describes the operation of a positive edge-triggered D flip-flop? a) If both inputs are HIGH, the output will toggle b) The output will follow the input on the leading edge of the clock c) When both inputs are LOW, an invalid state exists d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock
Answer: b Explanation: Edge-triggered flip-flop means the device will change state during the rising or falling edge of the clock pulse. The main phenomenon of the D flip-flop is that the o/p will follow the i/p when the enable pin is HIGH.
When is a flip-flop said to be transparent? a) When the Q output is opposite the input b) When the Q output follows the input c) When you can see through the IC packaging d) When the Q output is complementary of the input
Answer: b Explanation: Flip-flop have the property of responding immediately to the changes in its inputs. This property is called transparency.
For realisation of JK flip-flop from SR flip-flop, if J=0 & K=0 then the input is ___________ a) S=0, R=0 b) S=0, R=X c) S=X, R=0 d) S=X, R=X
Answer: b Explanation: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both the AND gates which results as S=0 & R=X(i.e. don't care).
If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________ a) SET b) RESET c) Clear d) Invalid
Answer: b Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.
Which of the following is correct for a D latch? a) The output toggles if one of the inputs is held HIGH b) Q output follows the input D when the enable is HIGH c) Only one of the inputs can be HIGH at a time d) The output complement follows the input when enabled
Answer: b Explanation: If the clock is HIGH then the D flip-flop operates and we know that input equals to output in case of D flip flop. It stores the value on the data line.
What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs? a) The output increases by 1 b) The output decreases by 1 c) The output word increases by 2 d) The output word decreases by 2
Answer: b Explanation: In an asynchronous counter, there isn't any clock input. The output of 1st flip-flop is given to second flip-flop as clock input. So, in case of binary down counter the output word decreases by 1.
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called a) Combinational circuits b) Sequential circuits c) Latches d) Flip-flops
Answer: b Explanation: In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it's known as combinational circuits.
One of the major drawbacks to the use of asynchronous counters is that ____________ a) Low-frequency applications are limited because of internal propagation delays b) High-frequency applications are limited because of internal propagation delays c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency counting applications d) Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications
Answer: b Explanation: One of the major drawbacks to the use of asynchronous counters is that High-frequency applications are limited because of internal propagation delays. Propagation delay refers to the amount of time taken in producing an output when the input is altered.
The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________ a) Parity error checking b) Ones catching c) Digital discrimination d) Digital filtering
Answer: b Explanation: Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0's catching.
Ripple counters are also called ____________ a) SSI counters b) Asynchronous counters c) Synchronous counters d) VLSI counters
Answer: b Explanation: Ripple counters are also called asynchronous counter. In Asynchronous counters, only the first flip-flop is connected to an external clock while the rest of the flip-flops have their preceding flip-flop output as clock to them.
The SR latch consists of ___________ a) 1 input b) 2 inputs c) 3 inputs d) 4 inputs
Answer: b Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The diagram of SR latch is shown below:
Latch is a device with ___________ a) One stable state b) Two stable state c) Three stable state d) Infinite stable states
Answer: b Explanation: Since, a latch works on the principal of bistable multivibrator. A Bistable multivibrator is one in which the circuit is stable in either of two states. It can be flipped from one state to the other state and vice-versa. So a latch has two stable states.
The S-R flip flop consist of ____________ a) 4 AND gates b) Two additional AND gates c) An additional clock input d) 3 AND gates
Answer: b Explanation: The S-R flip flop consist of two additional AND gates at the S and R inputs of S-R latch.
The full form of SR is ___________ a) System rated b) Set reset c) Set ready d) Set Rated
Answer: b Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.
What is the hold condition of a flip-flop? a) Both S and R inputs activated b) No active S or R input c) Only S is active d) Only R is active
Answer: b Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It is the No Change State or Memory Storage state if a flip-flop.
The sequential circuit is also called ___________ a) Flip-flop b) Latch c) Strobe d) Adder
Answer: b Explanation: The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.
Three decade counter would have ____________ a) 2 BCD counters b) 3 BCD counters c) 4 BCD counters d) 5 BCD counters
Answer: b Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it would require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.
To realise one flip-flop using another flip-flop along with a combinational circuit, known as ____________ a) PREVIOUS state decoder b) NEXT state decoder c) MIDDLE state decoder d) PRESENT state decoder
Answer: b Explanation: To realise one flip-flop using another flip-flop along with a combinational circuit, known as NEXT state decoder which acts as like a flip-flop.
The terminal count of a typical modulus-10 binary counter is ____________ a) 0000 b) 1010 c) 1001 d) 1111
Answer: c Explanation: A binary counter counts or produces the equivalent binary number depending on the cycles of the clock input. Modulus-10 means count from 0 to 9. So, terminal count is 9 (1001).
A counter circuit is usually constructed of ____________ a) A number of latches connected in cascade form b) A number of NAND gates connected in cascade form c) A number of flip-flops connected in cascade d) A number of NOR gates connected in cascade form
Answer: c Explanation: A counter circuit is usually constructed of a number of flip-flops connected in cascade. Preferably, JK Flip-flops are used to construct counters and registers.
Two stable states of latches are ___________ a) Astable & Monostable b) Low input & high output c) High output & low output d) Low output & high input
Answer: c Explanation: A latch has two stable states, following the principle of Bistable Multivibrator. There are two stable states of latches and these states are high-output and low-output.
A latch is an example of a ___________ a) Monostable multivibrator b) Astable multivibrator c) Bistable multivibrator d) 555 timer
Answer: c Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one in which the circuit is stable in either of two states. It can be flipped from one state to the other state and vice-versa.
When both inputs of a J-K flip-flop cycle, the output will ___________ a) Be invalid b) Change c) Not change d) Toggle
Answer: c Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.
Why do the D flip-flops receive its designation or nomenclature as 'Data Flip-flops'? a) Due to its capability to receive data from flip-flop b) Due to its capability to store data in flip-flop c) Due to its capability to transfer the data into flip-flop d) Due to erasing the data from the flip-flop
Answer: c Explanation: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value on the data line.
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________ a) The clock pulse is LOW b) The clock pulse is HIGH c) The clock pulse transitions from LOW to HIGH d) The clock pulse transitions from HIGH to LOW
Answer: c Explanation: Edge triggered device will follow when there is transition. It is a positive edge triggered when transition takes place from low to high, while, it is negative edge triggered when the transition takes place from high to low.
The difference between a flip-flop & latch is ____________ a) Both are same b) Flip-flop consist of an extra output c) Latches has one input but flip-flop has two d) Latch has two inputs but flip-flop has one
Answer: c Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an additional control input is provided to the latch.
For realisation of JK flip-flop from SR flip-flop, if J=1, K=0 & present state is 0(i.e. Q(n)=0) then excitation input will be ___________ a) S=0, R=1 b) S=X, R=0 c) S=1, R=0 d) S=1, R=1
Answer: c Explanation: If J=1, K=0 & present state is 0(i.e. Q(n)=0) then next state will be 1 which results excitation inputs as S=1 & R=0.
How many different states does a 3-bit asynchronous counter have? a) 2 b) 4 c) 8 d) 16
Answer: c Explanation: In a n-bit counter, the total number of states = 2n. Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.
How many natural states will there be in a 4-bit ripple counter? a) 4 b) 8 c) 16 d) 32
Answer: c Explanation: In an n-bit counter, the total number of states = 2n. Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
For realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from ___________ a) S and R b) R input c) J and K input d) D input
Answer: c Explanation: It is the reverse process of SR flip-flop to JK flip-flop. So, for realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from J and K.
With regard to a D latch ________ a) The Q output follows the D input when EN is LOW b) The Q output is opposite the D input when EN is LOW c) The Q output follows the D input when EN is HIGH d) The Q output is HIGH regardless of EN's input state
Answer: c Explanation: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop output follows the input. It stores the value on the data line.
Why latches are called a memory devices? a) It has capability to stare 8 bits of data b) It has internal memory of 4 bit c) It can store one bit of data d) It can store infinite amount of data
Answer: c Explanation: Latches can be memory devices, and can store one bit of data for as long as the device is powered. Once device is turned off, the memory gets refreshed.
One example of the use of an S-R flip-flop is as ____________ a) Racer b) Stable oscillator c) Binary storage register d) Transition pulse generator
Answer: c Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is referred to as binary storage element. It functions as memory storage during the No Change State.
The inputs of SR latch are ___________ a) x and y b) a and b c) s and r d) j and k
Answer: c Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The inputs of SR latch are s and r while outputs are q and q'. It is clear from the diagram:
Synchronous counter is a type of ____________ a) SSI counters b) LSI counters c) MSI counters d) VLSI counters
Answer: c Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous Counters, the clock pulse is supplied to all the flip-flops simultaneously.
The truth table for an S-R flip-flop has how many VALID entries? a) 1 b) 2 c) 3 d) 4
Answer: c Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs at both S and R being at 1.
One example of the use of an S-R flip-flop is as ___________ a) Transition pulse generator b) Racer c) Switch debouncer d) Astable oscillator
Answer: c Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices.
A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? a) AND or OR gates b) XOR or XNOR gates c) NOR or NAND gates d) AND or NOR gates
Answer: c Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-versa.
The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why? a) Because of inverted outputs b) Because of triggering functionality c) Because of cross-coupled connection d) Because of inverted outputs & triggering functionality
Answer: c Explanation: The cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they function in the absence of a clock pulse.
What is the significance of the J and K terminals on the J-K flip-flop? a) There is no known significance in their designations b) The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit d) All of the other letters of the alphabet are already in use
Answer: c Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the integrated circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the toggling of states.
What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of 'n' number of flip-flops? a) 0 to 2n b) 0 to 2n + 1 c) 0 to 2n - 1 d) 0 to 2n+1/2
Answer: c Explanation: The maximum possible range of bit-count specifically in n-bit binary counter consisting of 'n' number of flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will count till 22-1 = 3. Thus, it will count from 0 to 3.
How many types of flip-flops are? a) 2 b) 3 c) 4 d) 5
Answer: c Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.
When both inputs of SR latches are high, the latch goes ___________ a) Unstable b) Stable c) Metastable d) Bistable
Answer: c Explanation: When both gates are identical and this is "metastable", and the device will be in an undefined state for an indefinite period.
When both inputs of SR latches are low, the latch ___________ a) Q output goes high b) Q' output goes high c) It remains in its previously set or reset state d) it goes to its next set or reset state
Answer: c Explanation: When both inputs of SR latches are low, the latch remains in it's present state. There is no change in the output.
A NAND based S'-R' latch can be converted into S-R latch by placing ____________ a) A D latch at each of its input b) An inverter at each of its input c) It can never be converted d) Both a D latch and an inverter at its input
Answer: d Explanation: A NAND based S'-R' latch can be converted into S-R latch by placing either a D latch or an inverter at its input as it's operations will be complementary.
The characteristic equation of D-flip-flop implies that ___________ a) The next state is dependent on previous state b) The next state is dependent on present state c) The next state is independent of previous state d) The next state is independent of present state
Answer: d Explanation: A characteristic equation is needed when a specific gate requires a specific output in order to satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) = D; which indicates that the next state is independent of the present state.
Three cascaded decade counters will divide the input frequency by ____________ a) 10 b) 20 c) 100 d) 1000
Answer: d Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e. 10*10*10=1000 states.
Which of the following is correct for a gated D flip-flop? a) The output toggles if one of the inputs is held HIGH b) Only one of the inputs can be HIGH at a time c) The output complement follows the input when enabled d) Q output follows the input D when the enable is HIGH
Answer: d Explanation: If clock is high then the D flip-flop operate and we know that input is equals to output in case of D flip-flop. It stores the value on the data line.
What is an ambiguous condition in a NAND based S'-R' latch? a) S'=0, R'=1 b) S'=1, R'=0 c) S'=1, R'=1 d) S'=0, R'=0
Answer: d Explanation: In a NAND based S-R latch, If S'=0 & R'=0 then both the outputs (i.e. Q & Q') goes HIGH and this condition is called as ambiguous/forbidden state. This state is also known as an Invalid state as the system goes into an unexpected situation.
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature? a) Low input voltages b) Synchronous operation c) Gate impedance d) Cross coupling
Answer: d Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly connected to the other's output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.
A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states? a) CLK = NGT, D = 0 b) CLK = PGT, D = 0 c) CLOCK NGT, D = 1 d) CLOCK PGT, D = 1
Answer: d Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage output will be 1 and hence the stage will be changed.
Internal propagation delay of asynchronous counter is removed by ____________ a) Ripple counter b) Ring counter c) Modulus counter d) Synchronous counter
Answer: d Explanation: Propagation delay refers to the amount of time taken in producing an output when the input is altered. Internal propagation delay of asynchronous counter is removed by synchronous counter because clock input is given to each flip-flop individually in synchronous counter.
The outputs of SR latch are ___________ a) x and y b) a and b c) s and r d) q and q'
Answer: d Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two stable states. The inputs of SR latch are s and r while outputs are q and q'. It is clear from the diagram: digital-circuits-questions-answers-latches-q7.
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(total)) is ____________ a) 12 ms b) 24 ns c) 48 ns d) 60 ns
Answer: d Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits = 12ns * 5 = 60ns.
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________ a) 15 ns b) 30 ns c) 45 ns d) 60 ns
Answer: d Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15 * 4 = 60.
Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs? a) Gated JK-latch b) Gated SR-latch c) Gated T-latch d) Gated D-latch
Answer: d Explanation: Since, both inputs of the D flip-flop are connected through an inverter. And this causes reduction in the number of inputs.
A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________ a) Constantly LOW b) Constantly HIGH c) A 20 kHz square wave d) A 10 kHz square wave
Answer: d Explanation: The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.
What is one disadvantage of an S-R flip-flop? a) It has no Enable input b) It has a RACE condition c) It has no clock input d) Invalid State
Answer: d Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are high, which is referred to as Invalid State.
An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required? a) 1 b) 2 c) 8 d) 15
Answer: d Explanation: Transitional state is given by (2n - 1). Since, it's a 4-bit counter, therefore, transition states = 24 - 1 = 15. So, total transitional states are 15.
In D flip-flop, if clock input is HIGH & D=1, then output is ___________ a) 0 b) 1 c) Forbidden d) Toggle
a
In D flip-flop, if clock input is LOW, the D input ___________ a) Has no effect b) Goes high c) Goes low d) Has effect
a
On a J-K flip-flop, when is the flip-flop in a hold condition? a) J = 0, K = 0 b) J = 1, K = 0 c) J = 0, K = 1 d) J = 1, K = 1
a
The D flip-flop has ______ output/outputs. a) 2 b) 3 c) 4 d) 1
a
The D flip-flop has _______ input. a) 1 b) 2 c) 3 d) 4
a
A D flip-flop can be constructed from an ______ flip-flop. a) S-R b) J-K c) T d) S-K
a Explanation: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter between S and R and assigning the symbol D to the S input.
BCD counter is also known as ____________ a) Parallel counter b) Decade counter c) Synchronous counter d) VLSI counter
b
In D flip-flop, D stands for _____________ a) Distant b) Data c) Desired d) Delay
b
In digital logic, a counter is a device which ____________ a) Counts the number of outputs b) Stores the number of times a particular event or process has occurred c) Stores the number of times a clock pulse rises and falls d) Counts the number of inputs
b
How many flip-flops are in the 7475 IC? a) 2 b) 1 c) 4 d) 8
c 4 D flip-flops
In J-K flip-flop, "no change" condition appears when ___________ a) J = 1, K = 1 b) J = 1, K = 0 c) J = 0, K = 1 d) J = 0, K = 0
d
The parallel outputs of a counter circuit represent the _____________ a) Parallel data word b) Clock frequency c) Counter modulus d) Clock count
d
A 4-bit counter has a maximum modulus of ____________ a) 3 b) 6 c) 8 d) 16
d Explanation: In a n-bit counter, the total number of states = 2n. Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.