Random Access Memory

Double Data Rate 2 (DDR2)

A form of SDRAM, tiwce the speed of DDR, most commonly implemented as a 240-pin DIMM or a 200-pin SODIMM and not compatible with original DDR. Transfers data twice per block circle, bus clock speed between 200-533 MHz, bandwidth between 3200 and 8533 MB/s (an MT/s value: million transfers per second is often included when referring to the chip, ex) DDR2-800=800 million transfers per second.

Double Data Rate 3 (DDR3)

A form of SDRAM, twice the speed of DDR2, most commonly implemented as a 240-pin DIMM or a 204-pin SODIMM, not compatible with origincal DDR or DDR2. Bus clock speed between 400 and 1066 MHz, bandwidth between 6400 and 17066 MB/s. clock speed is one quarter of the bus clock speed, so chip would cycle four times per bus cycle, making it twice as fast as DDR2.

Double Data Rate 4 (DDR4)

A form of SDRAM, twice the speed of DDR3, currenly most recent variant, most commonly implemented as a 288-pin DIMM or a 256-pim SODIMM, not compatible with original DDR, DDR2, or DDR3. Bus clock speed between 1066 and 2133 MHz, bandwidth between 6400 and 17066 MB/s, transfers data twice per clock cycle.

Triple channel RAM

Implements three separate dedicated buses of 64 bits each, three physical chips would have their own channel, 6 physical chip will operate as pairs.The effective bus width is 192 bits, if there are only three physical chips, then each operates on its own channel when communicating to the processor, all available memory is still addressed separately so there are no conflicts in address space, but operations can now be performed simultaneously over each channel.

Parity vs. Non-Parity Memory

a method for discovering single-bit memory errors, not as effective as ECC memory as errors are only detected and not corrected, generally causes a stop error in the system, with any changes to data being lost. Its better to lose corrupt data then to store it. Predecessor to ECC memory, common in early memory chips that used high voltages resulting in high operating temps, read/write errors more common due to the higher temps, uses the same even/odd parity mechanism as ECC memory but limited to detection only.

Single channel RAM

data flows between the processor and RAM via pathways known as the memory bus, for modern systems: a single physical RAM chip operates over a 64-bit memory bus or a channel. The bus collectively made up of three pathways: Data, control and address. When using a single channel RAM, regardless the number of chips, all chips must share the single channel when communication with the processor. All available memory will be addressed separately so there are no conflicts in address space, but no operations can be performed simultaneously over the same channel.

Dual channel RAM

implements two separate dedicated buses of 64 bis each, if there are two physical chips, they each have their own channel, if there are four physical chips, they operate in pairs. Effective bus width is 128 bits.

Error checking and correcting (ECC) Memory

method for discovering and correcting single-bit memory errors, more reliable than non-ECC memory, but requires more processing (slower), used when the integrity of the data is more important than the speed of processing, visibly identifiable by a ninth module on the chip.

Synchronous Dynamic Random Access Memory (SDRAM)

refers to a performance characteristic, not the physical chip, almost all modern systems are using some for of SDRAM, clock speed is determined by the system bus speed, and most commonly implemented as a 168 pin DIMM for SDR (single data rate), 184 pins for DDR (double data rate).

Small Outline Dual Inline Memory Module (SODIMM)

refers to its smaller physical size/ not performance characteristics. It's commonly used in laptops, notebooks, or other limited space systems, chip dimensions are generally consistent, however the notch placement at the bottom varies with the type, easily replaceable and upgradeable provided the specifications are compatible.

Error correcting

uses a method known as parity, for every 8 bits written (1 byte), a 9th parity bit is also stored, for each byte the total number of 1's is summed: even parity=an even number of 1's (parity bit set to 0)/ odd parity= an odd number of 1's (parity bit set to 1). When that same data is subsequently read, the value of the parity bit is compared to the actual data, and if the parity bit matches the bit count, the data is assumed to be correct.