VLSI 1 - chapter 1

MPGA

mask-programmable gate arrays

MSI (incl. GEs of logic + bits of memory)

medium-scale integration. 10...100

algorithm design

meet data and/or signal processing requirements. 1) coming up with a collection of suitable alg. or computational paradigms. 2) cut down computational burden and memory requirements. 3) tradeoff between computational complexity and accuracy. 4) effects of finit word-length computation. 5) decide on number representation schemes. 6) evaluate alternatives. 7) quantify the minimum required comp. resources.

MOSFET

metal-oxide-semiconductor field-effect transistor

library elements (cell libraries)

-standard cell -megacell -macrocell

three different perspectives (Y-chart)

1) behavioral perspective 2) structural perspective 3) physical perspective

architecture desing (2 process stages)"

1) high-level design: results in a high-level block siagram taht includes datapaths, controller, memories, interfaces and key signals. 2) RTL (register-transfer level design): more detailled, circuit gets modeled as collection of storage elements interconnected by purely combinational subcircuits.

ASIC

Application-specific integrated circuit. desigend with a particular purpose. also known as "glue logic" (bus drivers, decvorders, MUX, registers, interfaces)

ASSP

Application-specific standard product. designed and optimized for a highly specific task(graphic accelerators, multimedia chips, ciphering/deciphering circuits,...)

Silicon foundry

operates a complete wafer processing line and that offers its manufacturing services to others.

Floorplanning

organizing the major circuit block into a rectangular area as small as possible, while limiting the effects of interconnect delays on the chip's performance

Fab-lite vendor

outsources the production of standard wafers processing steps but does the highly specialized steps (integr. sensors, actuators, ...) in-house (ex.: Sensirion, Luxtera,...)

Die size

poor metric -> use "GE" or "Transistor count" instead

PCB

printed circuit board

BJT

Bipolar Junction Transistor (either npn or pnp type)

hand-layout (procedure, reason, advantage, disadvantage)

procedure: using a CAD (computer-aided design). reason: dominante role in memory and analof circuit design. advantage: full control over layout, disadvatage:slow, cumbersome, prone to errors, expensive. archaic in digital design.

Architecture synthesis (5 major phases)

purly behavioral source code: 1) identify computational & storage requirements of the algorithm. 2) for each kind of sotrage & processing operation, select a suitable item from a virtual library. 3) est. a cycle based schedule for carrying out the alg. with those resources. 4) get a hardware organization, which is able to execute the res. working plan. spec. the architec. in terms of logic blocks, data registers, ... 5) keep track of data moves and operations for each clock cycle. translate all this into the necessary instr. for synthesis at the RTL level.

physical design verification

relies on a number of software tools: 1) DRC (design rule check) -> checks geometrical rules 2) manufacturability analysis -> searches for layout patterns likely to be detrimental (nachteilig) to fabrication yield 3) layout extraction obtains the actual circuit netlist in prepation of LVS 4) LVS (layout versus schematic) 5) post-layout timing verification 6) post-layout simulation

General-purpose IC

simple or generic purpose of an IC, such that it's been widly used (adder, FF, RAM, ROM, DSP). typically sold in huge quantities.

SSI (incl. GEs of logic + bits of memory)

small-scale integration. 1...10

ULSI (incl. GEs of logic + bits of memory)

ultra-large-scale integration. 1'000'000...

schematic entry

using a schematic editor which: - is capable of reading and writing both circuit diagrams and netlist - supports circuit concepts such as connectors, busses, node names, and instance identifiers.

test vector set

usually contains thousands or millions of stimuli and expected responses.

VLSI (incl. GEs of logic + bits of memory)

very-large-scale integration. 10'000...1'000'000

VC

virtual component: HDL synthesis package that is made available to others on a commercial basis. better knwon as: "intellectual property modules" <--> IP modules

Advantage of RTL

virtually technology-independent. --> as fabr. process developp very fast it is necessary to have portable designs.

GE of a Flip-Flop

~7 GE

BiCMOS

CMOS subcircuits combined with bipolar devices on a single chip

DFT

Design for test: improving the controllability and observabiity of inner circuits nodes by adding auxiliary circuitry on top of the payload logic.

ESL design automation

Electronic system-level design automation:

ECL

Emitter-coupled logic, non-saturating current switching circuits built on the basis of BJTs.

ESCL

Enhancement Source-Coupled Logic, similar to ECL but built from MOSFETs

FET

Field Effect Transistor (either n- or p- channel type)

GE

Gate equivalents-> two input NAND gate. corresponds to four MOSFETs in static CMOS

testbench

HDL code written dor driving the simulation of a model under test. not meant to be turned into a physical circuit

HDL

Hardware Description Language, s.a.: - VHDL - System Verilog

IC

Integrated Circuit incorporates and interconnects a multiude of miniature electronic devices (transistors) on a single piece of SD material (silicon)

IDM (business point of view)

Integrated device manufacture: creates designs and markets microchips AND wafer processing in-house in their own fab (ex.: Intel, Samsung, Texas Instruments, Toshiba,...)

MOS

Metal Oxid Semiconductor

RTL

Register transfer level: circuit is viewed as a network made up of storage elements held togheter by comb. building blocks

logic design (result?)

Result: complete set of gate-level schematics and/or netlists validated by electrical rule check (ERC), gate-level simulation, timing verification and power estimation.

Silicon vs Silicone

Silicon: Si, chemical element with atomic number 14 Silicone: broad family of polymers of Si.

SoC

System-on-a-Chip

TTL

Transistor Transistor Logic. made up of BJTs and passive devices. 5V supply voltage.

structured ASIC

Type: semi-custom IC. a lot of metal layers. transistors are preconnected into small generic subcircuits (NANDs,MUXs, AOI gates, full-adders, LUT)

Gate array (channeled gate array)

Type: semi-custom IC. long rows of transistors which can be individually connected by metal lines.

sea-of-gates

Type: semi-custom IC. new idea for gate arrays. channelless.

fabric

Type: semi-custom IC. standardize metal layers as much as possible. subcircuits are pieced together by short metal straps, called jumper.

USIC

User-specific integrated circuit. opposit of ASSP, designed for a single purpose and optimized for a single customer. control of innovation and protection of proprietary know-how.

VHDL

Very High Speed Integrated Circuit Hardware Description Language.

well

a volume that accommodates MOSFETs of identical polarity. doping is opposite to the source and drain islands embedded.

BIST

build-in self test

standard parts (COTS)

commercial off-the-shelf component. a catalog part with no customization of the circuit hardware whatsoever.

CMOS

complementary MOS where pairs of n- and p-channel MOSFETs cooperate in each logic gate. compare also: static CMOS, dynamic CMOS

pad

connector on a die that is intended to be wired or otherwise electrically connected to a package pin.

physical design

contains all issues of arranging the multitude of subcircuits and devices along with their interconnections on a piece of semiconductor material.

netlist

data structure that captures what instance make up for a (sub)circuit and how they are interconnected.

DRC

design rule check: examines conformity of layout with geometric rules imposed by the target process

fabless vendor

develops and markets proprietary SD comp. but has their manufacturing commissioned to an independent silicon foundry. (ex.: Altera, Actel, Broadcom, Nvidia, Xilinx)

DSP

digital signal processor

ERC

electric rule check

cell-libraries

elementary subcircuits collected together.

Circuit complexity

expressed by GE of logic and storage capacity in bits

Intellecutal property (IP) vendor

fabless company which dev. hardware subfunctions and to license them to others. (ex.: ARM, Faraday, Sci-worx, Synopsys)

Full-custom ICs

fabrication point of view. all layers are patterned according to user specification. needs a full set of lithographic photomasks.

Semi-custom ICs

fabrication point of view. only a small subset of fabrication layers is unique to each design. master-wavers are used to build up the common part of the design.

FPGA

field-programmable gate arrays.

FPL

field-programmable logic. soft-hardware

chip assembly

final phase where the global wires running between padframe and core get routed.

automatic circuit synthesis

formal description of an entire chip. synthesis models are established using a text editor by using a hardware description language (HDL) such as VHDL or System Verilog. Output: gate-level netlist as a start-point for place and route.

levels of abstraction (5) (Y-chart)

from top to down: 1) system 2) architecture 3) register transfer 4) logic (aka gate-level) 5) electrical

die

fully processed but unencapsulated IC

Logic synthesis

generation of combinational networks and finite sate machines (FSM). synthesis tools accept logic equation build from operators s.a. not,and, nor, or, truth tables, state graphs ,...

System-level design

important decisions: 1) specify functionality, operating conditions, characteristics 2) partition system's functionality into subtasks 3) explore alternative hardware and software tradeoffs 4) make or buy decisions for all building blocks 5) decide on data format, operating modes, exception handling proc,... 6) define, model evaluate and refine subtasks from a behavioral perspecitve

ISC

in-system configuration. related to FPL. most of today's product families allow for in-system configuration.

turnaround time

lapse (Ablauf) of time from coming up with a finalized set of design data until physical samples become available for testing.

LSI (incl. GEs of logic + bits of memory)

large-scale integration. 100...10'000

LVS

layout versus schematic: compares the actual netlist against the desired one