Computer Architecture Ch 8 Quiz
Cache memory hit ratios of ________ percent and above are common with just a small amount of cache.
90
What are the slowest steps in the instruction fetch-execute cycle?
Slowest steps are those that require memory access.
There are several factors that determine the number of instructions that a computer can perform in a second. Which of the following is NOT a factor?
Word Size
The __________ must be designed to assure that each step of the instruction cycle has time to complete before the results are required by the next step.
clock cycle
The ___________ unit contains the arithmetic/logic unit and the portion of the control unit that identifies and controls the steps that comprise the execution part for each different instruction.
execution
The use of fixed-length, fixed-format instruction words with the op code and address fields in the same position for every instruction would allow instructions to be fetched and decoded
independently and in parallel.
CPU architecture is defined by the basic characteristics and major features of the CPU. "CPU architecture" is sometimes called
instruction set architecture
Another method for increasing the effective rate of memory access is to divide memory into parts, called, _____________ so that it is possible to access more than one location at a time.
memory interleaving
What does "locality of reference" mean?
most memory references are confined to one or a few small regions of memory
Computers that have multiple CPUs within a single computer, sharing some or all of the system's memory and I/O facilities, are called______________, or sometimes tightly coupled systems.
multiprocessor systems
Overlapping instructions—so that more than one instruction is being worked on at a time—is known as the
pipelining method.
A(n) _____________ processor is one that can complete an instruction with each clock tick.
scalar
Instruction reordering makes it possible to provide parallel pipelines, with duplicate CPU logic, so that multiple instructions can actually be executed
simultaneously.
When a cache miss occurs, however, there is a time delay while new data is moved to the cache. The time to move data to the cache is called _____________ time.
stall
Which of the following is not a specific execution unit?
steering unit