CPE 133 Mealy (Verilog)
This experiment used a clock divider to slow down the dev board's clock to something around 2Hz. Show how exactly you slowed down the clock, including any associated calculations.
100,000,000 Hz / 50,000,000 = 2Hz, to divide by 50,000,000 we need the clk_divider_nbit, count[n] bit to happen every 50,000,000 ticks, since it is binary, n should satisfy, 2^n ~= 50,000,000. n=24 gave us the closest and best results.
Show a closed form formula that relates the data width the number range for an unsigned binary number. Make sure you use an accepted format for specifying number ranges.
2-bits 0 to 3, 3-bits 0 to 7, 4-bits 0 to 15... We can say that for n-bits, the range will be [0, (2^(n)) - 1]
Show a closed form formula that relates the data width the number range for a signed binary number in RC format. Make sure you use an accepted format for specifying number ranges.
3-bits -4 to 3, 4-bits -8 to 7, 5-bits -16 to 15... We can say that for n-bits, the range will be [-(2^(n-1)), (2^(n-1)) - 1]
Sequential circuits are referred to as having "state". In your own words, briefly describe what exactly that means.
A State, broken down into its simplest explanation, is nothing more than "the value a circuit it is currently remembering". It is the present values a circuit has stored that define a circuit's present/current state.
The always block contains a "sensitivity list". Briefly describe what this is. Also, state what you should generally place in the sensitivity list.
A sensitivity list controls when all statements in the always block will start to be evaluated. Generally, put all inputs into the sensitivity list.
The state registers in a FSM are considered a synchronous circuit. Briefly describe what this means in context of the FSM.
A synchronous circuit is one that has states that change synchronized by a signal clock, so in the context of the FSM, the states switch in time with the CLK signal.
In your own words, what is a test vector and what entity generates the vectors for your testbench?
A test vector is a set of inputs for testing new hardware designs, and in this lab the vectors that were generated were by the designer of the circuit.
An XNOR gate is often referred to as an "equivalence gate". Briefly explain how it would get such a name.
An XNOR gate outputs a 1 when the inputs are the same, and it outputs a 0 if the inputs are different, which gives it the name equivalence.
Briefly describe why an AND gate is not functionally complete.
An and gate is not functionally complete because it isn't possible to create a gate that inverts with and AND gate.
We all know that the well-known hallmark of a comparator is that it uses EXOR-type gates in its implementation. Does the development board you're using actually use EXOR-type gates in your design? Briefly but completely explain.
Basically, when it comes down to it everything just uses LUTS.
Consider two different HDL models that are functionally equivalent; in particular, they are mostly the same except for the notion that one used structural modeling and the other implemented a similar set of modules but did not use structural modeling. Would expect the synthesized circuit based on these models to use the equivalent amount of resources or will one approach use more or less resources. Support your answer with intelligent commentary.
Even though the RCA high level circuit consists of half and full adders, it still has the same logic gates that would be used if the RCA was created without structural modeling. Although the structural modeling approach is ideal because modules can be reused and it's easier to follow, the synthesized circuits should end up using the equivalent amount of resources.
Explicitly show how you can obtain an AND function from an OR gates. In your own writing, show both the derivation and the resulting circuit element.
F = A + B ~(~F) = ~(~(A + B)) => F = ~(~A~B)
Explicitly show how you can obtain an OR function from an AND gate. In your own writing, show both the derivation and the resulting circuit element.
F = AB ~(~F) = ~(~(AB)) => F = ~(~A + ~B)
Based on the previous question, you probably see that modeling comparators of any size is no big deal using an HDL. Why then did this lab activity ask that you model a larger comparator using two smaller comparators?
Having 2 instead of one comparator helps us understand hierarchical design and can help us make a truth table if we need to.
Write a formula in closed for that describes the number of gates in a RCA as a function of the bitwidth of the RCA. Recall that the LSB of the RCA is a HA. For this question, assume the FA and HA are in reduced form (not in standard SOP form).
I'll start with setting: number of bits = N Then I'll conclude: 6(N-1)+2
The output of this circuit arbitrarily showed dashes when the number was not valid. Is there an output that would have been more appropriate in this activity? Briefly state your thoughts on this matter.
Ideally we would be able to show the actual value of these non-valid numbers but it exceeds the number of bits we were using for the experiment. However, the dashes showing could be changed to something to better 'error' or a more informative display value.
HDL allows you to write complex if statements (if statements containing many conditions) as well as nested if statements. Make a statement about the complexity of an "if" statement and the size of the hardware generated by such statements.
If statements vary greatly in their complexity, the more variables (and more bit-widths) for the statements the more complex. And nesting statements does not make it that much more complex besides chaining the statements.
Briefly explain what it would mean if the output of your simulation did not match the outputs on hardware for the same inputs?
If the outputs of the simulation don't match the outputs on the hardware, that means either one was implemented wrong or even both were implemented wrong
Did the FSM model you used for the circuit in this lab activity use some form of illegal state recovery? Briefly explain.
If we did not use default for our case statement we would have had to use illegal state recovery, but we did not have to since we did that, we only made the amount of states we wanted.
In general, does the number of levels of a particular design affect the resources required to implement that design using an HDL and implementing that circuit on an FPGA? Briefly but fully explain.
In general, no. It has to do with how complex the modules are.
One of the important design approaches in modeling digital circuits is to use a LUT (decoder) whenever possible. Briefly describe why this is a good approach.
In its most basic state a LUT is a table that determines what the output is for any given amount of inputs. A LUT can be implemented where whatever behavior you get by interconnecting any number of gates without feedback paths which is what makes it a good approach.
This experiment only asked you to draw a state diagram using six states. Briefly describe how many states the FSM in this experiment actually contains.
It actually contains 16 (0 through 15) states but can move between them in both directions.
Briefly describe the notion of concurrency in digital circuit design.
It basically means that an infinite amount of statements, that are modeling hardware, can be executed at the same time because of the parallelism of digital design.
Describe an application where sequence detectors could potentially be useful.
It can be used in scenarios where there is a lot of noise in the signal. If there's a lot of noise the circuit might misunderstand the data; for instance, it might misinterpret 1011 as 1111 and signal the end of the packet, but this can be avoided with a sequence detector.
Briefly describe the particular attribute of a digital circuit (not of an HDL model) that gives the circuit the ability to store data.
It can store data by feeding back the output as an input, or in other words make the circuit's output also and input.
From your state diagram, what would happen if both the ODD and EVEN input were simultaneously asserted?
It depends on which number you're on when you press both. If you on an odd number when you press both it will cycle through the odd numbers and vice versa for even numbers.
Briefly describe how the full adder is somewhat limited in doing math operations.
It is somewhat limited because it needs a carry-in to do any sort of math operation. Also you need more if you want to add anything more than 3 bits.
If you were not able to use a decoder in this experiment, how many concurrent signal assignments would you have needed to implement the segments portion of the seven segment display? Briefly explain.
It would need to have an equation of 7 variables (ABCDEFG) and have a sum of 10 products for the numbers it can handle. This is because without a decoder you have to represent every number in a different way with the 7-bit number to have all the inputs proper for the number display.
The always block is one of Verilog's concurrent statements. But, the always block contains only sequential statements in the body of the always block. Describe how this seemingly oxymoron is actually possible.
It's basically because we have a clock signal, and that's what makes it sequential.
Briefly describe why is it a good idea to avoid modifying previously designed modules in your new design?
It's because the previously designed modules have been tested and work, but as soon as you edit it it's totally different and doesn't work anymore. Therefore, it's often better to just start a new design module.
In computer programming, briefly describe why it is the best idea to use an unsigned integer type when it is known that the value will never be negative.
It's better to use an unsigned integer when the value won't be negative because it can hold larger values than a signed integer.
In your own words, briefly but completely explain why the circuit in this lab activity is referred to as a "ripple carry adder".
It's referred to as the "ripple carry adder" because the carry can "ripple" through every module inside of it.
Briefly describe the symmetry present in both the state diagram and HDL model of this FSM.
It's symmetric, ignoring the reset, because each state has the same pattern of transitions around it going to the next states. For example, the normal up/down and the even/odd up/down are basically the same at each state.
Often we refer to a design as a "flat" design. In terms of HDL modeling, briefly but fully describe what that term refers to.
Making zero the number of levels in a design. A way to look at it is minimizing the amount levels of black box diagrams needed to make the design function as needed. (Avoiding a super deep inception of modules).
Mealy-type FSM are able to "react" more quickly than Moore-type FSMs. Briefly describe what characteristic of a Mealy-type FSM makes this the case.
Mealy-type outputs a signal based on external inputs. This can be represented in state diagrams through attaching output values to the arrow transitions, thus condensing the number of states that need to be drawn. If similar behavior were to be done on a Moore-type model, another state would have to be added, whereas in a Mealy-type model it could be combined into the arrow transition.
Briefly explain what characteristic of a circuit makes it a "mixed logic" circuit?
Mixed logic is an encumberment of positive and negative logic because the it depends on when the circuit demands the interpretation of both 1 and 0 being active state.
We often use hexadecimal notation in digital-land. Can you use hex notation to represent signed binary numbers in RC format? Briefly explain.
No you can't because you'd have no idea if the number in hex was the actually number or a different number because it's signed binary.
Verilog always blocks contain "sensitivity lists". If you modeled two MUXes in Verilog that were identical except for the fact that one MUX included the select signals in the sensitivity list, and the other not, would the hardware generated by these two MUXes be identical? Briefly explain.
No, they would not be identical. The mux with SEL in the sensitivity list would update its D_OUT at any change of the SEL value, where as the one without would only change the D_OUT value if any of the other values change, or at that point you may want a clk signal.
In computer programming, briefly describe what happens when a mathematical operation exceeds the ranges for the data types associated with that operation? Does the programmer typically know the range has been exceeded?
Normally the MSB is lost and only the bits within the bit with are shown, so the programmer doesn't always know the range has been exceeded.
In the previous question, briefly describe what exactly the term "react" refers to?
React refers to the state machine detecting a change in the input and doing some action in response; i.e. the outputs are a function of the inputs.
From your HDL model, what would happen if any other input is asserted at the same time as the RESET input?
Reset has precedence because it is asynchronous so it will always reset and go to state 0.
Briefly describe what the term "sequential" refers to in the term "sequential circuit".
Sequential refers to the fact that the outputs are based on a sequence of inputs.
How many logic gates would it require to implement the 5-bit RCA using discrete logic? For this problem assume the logic is in standard SOP.
Since a half-adder requires 2 gates and a full-adder requires 6 gates, and a 5-bit RCA uses 4 full-adders and 1 half adder: it requires 26 gates.
Briefly but completely describe the three basic modules of a FSM. Make sure your description includes which of the two classes of digital circuits the modules represent.
State Decoder- shows what happens based off of the previous state and the external input. Register- stores the data so that it can either be fed back into the next state decoder or go into the output. Output Decoder- can either just use the previous state for an output or it can use the external input as well, this determines what kind of output it is (Moore vs Mealy).
What is a really good reason that I don't put in the effort to design a subtractor in addition to my RCA?
Subtracting A and B would be thought of as A + (-B) which is just addition with a negative number, so it's more work and unnecessary. It's easier to approach it by adding A to the 2's complement of B.
Briefly comment on which form (SOP or POS) of the HA & FA was easier to design and implement.
Sum of Products was easier to implement in general because each of the products is easily seen as the inverse (complimented) version of the combination of input bits for the desired outputs.
Given two FSMs that perform the same basic function, a Mealy-type model typically has fewer states than Moore-type models. Briefly describe why that is generally the case.
That is generally the case because Moore outputs take more states to assign the output since a Mealy output can assign a condition during a transition to another state.
Similar to 7-segment displays, there are also 14-segment displays out there in the real world. Briefly describe the main purpose served by 14-segment displays.
The 14-segment display is better because it includes four diagonal and two vertical segments with the middle segment broken in half. This allows you to be able to display all numbers, letters, and most regular symbols for more variety in the display message.
How many clock cycles did your circuit require to complete the sort? Your answer to this question should address best and worst case scenarios (if your approach had both scenarios).
The best case scenario had one clock cycles, but the worst case scenario was eight clock cycles.
For a RCA, the result could be available immediately, or the result could be delayed. Describe a case where the result is available immediately and also describe a case where the delay is the "worst case". State how long the worst case is in terms of "gate delays".
The best case scenario would be that there are no carries. Worst case scenario there's a carry on every addition and the AND gate is activated with every single adder.
Briefly describe the FSM output-type classification of the decimal output you used in this experiment.
The decimal output is a Moore output because it only depends on state while it's counting.
Briefly describe the difference between a flip-flop and a latch.
The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do (or at least after a small propagation delay). A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high.
Briefly describe the FSM output-type classification of the stone-age unary output you used in the previous experiment and then in this experiment.
The difference is that the last experiment was a Moore output because the output was solely based on the state, but this experiment was also based on an external factor making it a Mealy output.
There are many sort algorithms out there. State two reasons why you would choose one over another. For this problem, consider your task is to implement the problems in hardware.
The first reason would be that you would choose a faster algorithm that the time it takes to execute the sort increases at a slower rate as more elements to be sorted increases than the other algorithm. Next, another reason would be to choose the an algorithm that takes less space and hardware than the other which saves costs.
Self-correcting hardware is a great feature in digital design. Briefly describe what the term "illegal state recovery" means and the specific condition that it attempts to avoid.
The illegal state recovery is when an FSM has unused states and corrects itself automatically if it switches to one of them. This can be done by including conditions in the unused states that redirects the FSM to the correct sequence. It attempts to avoid the hang states.
Slower clock speeds of any circuit are generally considered better because they save power. Briefly describe the main factor in deciding the minimum clock speed for your FSM and still have it do the job you need it to do.
The main factor in deciding the minimum clock speed is the number of states that the FSM has.
Sequential circuits are known to contain memory, but it is not clear from the word "sequential" where the memory comes from. For this problem, briefly describe the relation between the word "sequential" and memory.
The memory is related to the state.
For a given bit-width, does the number of unique numbers in an unsigned binary and signed binary number in RC format differ? Briefly explain.
The number does not differ because the max magnitude of the signed binary numbers in RC format is half the unsigned binary numbers. The signed binary numbers can be either positive or negative.
Sorting of course can also be done in software. If would be hard to state whether the algorithm you implemented in hardware in this experiment would run faster than the same algorithm implemented in software. Just for kicks, name a few parameters that you would need to consider if you were to make such a comparison.
The number of compare circuits, the number of data storage elements/memory available, the processor, and the clock cycle.
Relating to the previous problem, if the system clock frequency was 100MHz, how much time was required to complete the complete sort operation for the best and least case scenarios. Show your calculations for this problem. Assume your circuit is not using a clock divider. Don't even think of not writing your answer using engineering notation.
The time it takes to calculate the product is 1*10^-8 seconds, best case scenario, and 8*10^-8 seconds for worse case scenarios when at 100MHz clock speed.
The univ_sseg.v module you used in this lab activity seemed to do a great job of simultaneously displaying more than one number at a time on the development board's seven-segment displays. But you were previously told that the displays could only show no more than one number at a time. Briefly explain what is going on.
The univ_sseg.v can seem like it's displaying more than one anode at a time because the anode being lit switches between other anodes so fast that our eyes can't see it.
If someone told you they encoded their FSM using eight flip-flops, would you know how many unique states were in their state diagram? Briefly explain.
There could be up to 256 unique states, but there's no way to know how many unique states there are based on the number of flip-flops.
Briefly describe the relation, if any, between a sequential circuit in digital design and a sequential statement in Verilog?
There is no relationship between the two because they are 2 very different concepts.
Briefly state why it is that state diagrams never includes clock signals.
They never include clock signals because it is implied that each transition or change of state is happening on the clock signal since a state diagram is showing the synchronous elements mostly and FSMs are clock signal dependent. When they aren't synchronous (for RESET) it still doesn't effect the effectiveness of the diagram to have them as well, as long as you know what is synchronous and what is not.
How many rows were there be in a truth table for a 32-bit RCA? Would it be feasible to design a 32-bit RCA using a truth table?
This would require the equation 2^64 = 1.84 x 10^19 rows, which is not a feasible design for the 32-bit RCA using truth table.
Using the development board under the conditions stated in this lab activity, would it have been possible to design an adder/subtractor unit based on 9-bit signed binary numbers (RC format)? The problem here is that you run out of switches to support 18-bit number. Consider all possibilities and fully explain your answer.
To avoid the switch problem we could use buttons perhaps. But for the most part, the fact that our modules used are modular and parameterizable then we can change some things around to account for the extra bits.
In your own words, provide a complete written description of how the circuit you designed in this experiment operates. Be sure to reference the block diagram for your circuit. This description should be more than a detailed description of the state diagram.
To be able to move around the numbers while sorting and remember the states, we need to use registers as memory, and then use an FSM controlling muxes, that decide what to input into the registers. This FSM gets its status from three comparators that compare the 4 values to each other, giving the necessary information to control the circuit.
Briefly describe the steps necessary in order to extend this design to 8-bit signed binary numbers (once again, assume your development board and provided modules are not limiting factors).
We first we would have to change the instantiations of all modules to work better also, then we would need to change the bit number we use for our validity checking and control.
Briefly described how you verified your circuit in this experiment was working properly.
We tested when one input was a 1, the sum was 1, and when two or three inputs were a 1 the CO was 1 and so on. The lights on either side of the board, for each type of equation, were the same so we could visually see that POS and SOP are functionally equivalent.
If you needed to extend the RCA from this lab activity to a 10-bit RCA by using a structural model with two 5-bit RCAs, what changes would you need to apply to the 5-bit RCA?
We would need to get rid of the first Half Adder of the second 5-bit RCA and then we could chain them together to allow for 2, 10-bit inputs, we would still have the same ending CO which would tell the validity of the sum.
Describe the modifications you would need to make to the circuit in this lab activity is you needed a 2*A or A-B circuit instead of the A+B or A-B. Do not use a shift register in your solution.
We would still need a mux to decide between adding A to itself in the RCA, or A + -(B) we would still need to use a 2's comp for B to subtract but the functionality would still be the same.
Quite often in digital design, there are boundary condition issues you need to deal with. What this means to me is that 98% of the errors I make in a design are with a boundary condition. This lab activity also has a boundary condition that essentially renders the result invalid even though it passes our simple validity checker. Briefly describe this boundary condition. HINT: the notion that it is a boundary condition roughly means that is has something to do with the far end of the given number range for the RC numbers.
When adding two positive numbers or two negative numbers that can be represented in 5-bits, sometimes it overflows to more bits than we started with so it is invalid since whatever is displaying cannot be valid in that amount of bits.
Briefly describe why state diagrams generally do not include any notion of a clock signal.
When working with state diagrams each transition is happening on a clock signal
In your own words, briefly describe the advantage(s) of using a behavioral model as opposed to a gate-level implementation of the comparator.
When you use a behavioral model you are free from using the underlying logic of a module and you can use statements to describe a circuit, which can be easier and less confusing.
Briefly describe how you could configure the two full adders to become a two-bit adder.
Wire the CO of the first into the Cin of the second adder to be able to carry it over and add with another A and B input.
Briefly describe whether you could have used a decoder for the "logic box" portion of this lab? Also, provide a justification as to why you would not and/or did not use a decoder for this part of the circuit.
With our current knowledge we would be able to use a decoder like before, but we would need to have a 6 bit input and a massive truth table and it would be highly inefficient and there would be way too much room for error putting in all the different possible combinations, that's why we must use higher levels of modules and logic.
Do the various module instantiations in a HDL model operate in a concurrent manner? Briefly explain why or why not.
Yes because Vivado takes blocks of concurrent code and puts them together when the modules are instantiated, so since the pieces of the model are executed concurrently the whole model will be concurrent.
Can an 8-bit binary number in unsigned format ever be an odd number but have even parity? Briefly explain.
Yes because parity doesn't deal with even or odd numbers. It just counts the number of set bits in a group.
Can signed binary numbers in RC format have the notion of parity associated with them? Briefly explain your answer.
Yes because parity refers to the number of bits that have been set.
mixed logic circuit
a circuit that contains both negative and positive logic signals
functionally complete
a gate that can be used to implement and, or and inversion functionality
model
a representation or description of something
behavioral modeling
describing a digital circuit with its desired behavior rather than modeling it with low-level logic elements such as gates
Write a closed form formula that relates the maximum number of unique states in a sequential circuit to the number of 1-bit storage elements in the sequential circuit.
f(x) = 2^x
difference between flip flop and latch
flip flops are edge sensitive while latches are level sensitive. both are 1-bit storage elements
Since you now know there are many ways to implement digital circuits, describe some possible parameters involved in ascertaining the "best" way.
functionally equivalent.
Write a closed form formula that shows how many storage elements (n) would need to implement a circuit requiring Q unique states. This formula should include a floor or ceiling function.
n = ceiling(logQ) or n = log2(Q) (not sure)
radix
number of symbols in the ordered set of symbols for a given number system
functionally equivalent
some input/output relationship, but different equations
state of a circuit
the value being stored in the circuits memory elements
