CS 330 Chapter 14

1. The ARM architecture supports _______ execution modes. A. 2 B. 8 C. 11 D. 7

7

1. _________ is a pipeline hazard. A. Control B. Resource C. Data D. All of the above

All of the above

1. __________ are bits set by the processor hardware as the result of operations. A. MIPS B. Condition codes C. Stacks D. PSWs

Condition codes

__________ registers are used by the control unit to control the operation of the processor and by privileged operating system programs to control the execution of programs.

Control and status

1. ________ registers may be used only to hold data and cannot be employed in the calculation of an operand address. A. General purpose B. Data C. Address D. Condition code

Data

13. An interrupt is generated from software and it is provoked by the execution of an instruction.

F

2. The control unit (CU) does the actual computation or processing of data.

F

5. The allocation of control information between registers and memory are not considered to be a key design issue.

F

8. A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.

F

__________ or fetch overlap is where, while the second stage is executing the instruction, the first stage takes advantage of any unused memory cycles to fetch and buffer the next instruction.

Instruction prefetch

1. The _________ contains a word of data to be written to memory or the word most recently read. A. MAR B. PC C. MBR D. IR

MBR

__________ is a process where new inputs are accepted at one end before previously accepted inputs appear as outputs at the other end.

Pipelining

1. __________ are a set of storage locations. A. Processors B. PSWs C. Registers D. Control units

Registers

10. The predict-never-taken approach is the most popular of all the branch prediction methods.

T

11. It is possible to improve pipeline performance by automatically rearranging instructions within a program so that branch instructions occur later than actually desired.

T

12. Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions can be serviced and later resumed.

T

14. While the processor is in user mode the program being executed is unable to access protected system resources or to change mode, other than by causing an exception to occur.

T

15. The exception modes have full access to system resources and can change modes freely.

T

3. Within the processor there is a set of registers that function as a level of memory above main memory and cache in the hierarchy.

T

4. Condition codes facilitate multiway branches.

T

6. Instruction pipelining is a powerful technique for enhancing performance but requires careful design to achieve optimum results with reasonable complexity.

T

7. The cycle time of an instruction pipeline is the time needed to advance a set of instructions one stage through the pipeline.

T

9. One of the major problems in designing an instruction pipeline is assuring a steady flow of instructions to the initial stages of the pipeline.

T

The processor needs to store instructions and data temporarily while an instruction is being executed.

T

1. ________ is used for debugging. A. Direction flag B. Alignment check C. Trap flag D. Identification flag

Trap flag

_________ registers enable the machine or assembly language programmer to minimize main memory references by optimizing use of registers.

User-visible

1. The _________ is a small cache memory associated with the instruction fetch stage of the pipeline. A. dynamic branch B. loop table C. branch history table D. flag

branch history table

A _________, also known as a branch hazard, occurs when the pipeline makes the wrong decision on a branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.

control hazard

The ________ controls the movement of data and instructions into and out of the processor. A. control unit B. ALU C. shifter D. branch

control unit

The major components of the processor are an arithmetic and logic unit (ALU) and a __________.

control unit (CU)

1. A ________ hazard occurs when there is a conflict in the access of an operand location. A. resource B. data C. structural D. control

data

Data are exchanged with the processor from external memory through a _________.

data bus

1. The ________ determines the opcode and the operand specifiers. A. decode instruction B. fetch operands C. calculate operands D. execute instruction

decode instruction

Two classes of events cause the x86 to suspend execution of the current instruction stream and respond to the event: interrupts and ________.

exceptions

1. The _________ stage includes ALU operations, cache access, and register update. A. decode B. execute C. fetch D. write back

execute

A processor must: fetch instruction, interpret instruction, process data, write data, and _________.

fetch data

The _________ element is needed to transfer data between the various registers and the ALU.

internal processor bus

An instruction cycle includes the following stages: fetch, execute, and _______.

interrupt

1. A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence. A. loop buffer B. delayed branch C. multiple stream D. branch prediction

loop buffer

A __________ occurs when the pipeline, or some portion of the pipeline, must stall because conditions do not permit continued execution.

pipeline hazard

1. The _________ contains the address of an instruction to be fetched. A. instruction register B. memory address register C. memory buffer register D. program counter

program counter

Many processor designs include a register or set of registers often known as the _________ that contain status information and condition codes.

program status word (PSW)

The ________ flag allows the programmer to disable debug exceptions so that the instruction can be restarted after a debug exception without immediately causing another debug exception.

resume

1. The OS usually runs in ________. A. supervisor mode B. abort mode C. undefined mode D. fast interrupt mode

supervisor mode

The three types of data hazards are: read after write (RAW), write after write (WAW), and _________.

write after read (WAR)