ECE 2720 final
How many bits does the N register in the IJVM architecture hold?
1
How many bits does the Z register in the IJVM architecture hold?
1
What is the frame rate of the USB bus?
1 ms
What is the maximum number of devices that can be attached to a USB's root hub?
127
What was the maximum throughput of the ISA Bus?
16.66 MB/s
What decade saw the advent of the Operating System?
1960s
What decade saw the advent of the RISC machines?
1980s
What was the maximum throughput of the EISA Bus?
33.33 MB/s
How many wires does the USB cable have?
4
What was the maximum throughput of the PCI Bus?
528 MB/s
What is the speed of the PCI bus?
66 MHz
How many bits does the MBR in the IJVM architecture hold?
8 bits
What is the maximum data width of the PCI Bus?
8 bytes
What was the speed the ISA bus?
8.33 MHz
What is the purpose of the MBR register in the IJVM architecture?
: It is the memory branch register which holds the instruction and the instruction parameters.
Who standardized and named the ISA bus?
A consortium of PC Manufacturers
An [a] chip is a peripheral chip we discussed which could be used to store a digital sampling of a song.
ADC
ADD IC PACKAGE PICTURES HERE
ADD IC PACKAGE PICTURES HERE
What is the unit in a CPU called which would perform an operation such as addition or ORing?
ALU
In the IJVM achitecture, what's the purpose of the "control store"?
Aka the ROM. It is the memory that holds the microprogram. Contains 512 wors, each a 36-bit microinstruction
How is an embedded system different than a computer? How is it the same?
An embedded computer is the same in that it executes a set of instructions given to it. It is different in that it only performs a small portion and relies on the computer, where the computer handles all of the data or instructions.
Which category of CPU would a DSP processor fall into?
Application specific
. I have asked my class of 16 to help me fill out 100 identical forms. I tell them what to write in the first blank and they write it down. Then I tell them what to write on the second blank, and they fill that out. This is repeated until all 100 forms are complete. What type of computer is most analogous to this process?
Array Processor
What was "Level 4" for the six-level computer as discussed in class?
Assembly Language level
What was the purpose of "Batch Jobs"? How did they relate to the evolution of operating systems?
Batch jobs are executed by the computer without requiring the user to enter them. They made using computers easier to users.
WHy is the invention of the EEPROM so important to our use of electronics
Because its erasable and can be done so electronically.
Who created the first working calculating machine, which could perform addition and subtraction?
Blaise Pascal
What type transfer adds a control line which allows a device to transmit a sequence of data words, one each clock cycle, instead of having to start the read cycle all over again for each data word in the sequence? (Same as above Q)
Block transfer
what type of transfer adds a control line which allows a device to transmit a sequence of data words instead of having to restart the read cycle
Block transfer
Name three countries that worked on developing computers before WWII ended as I discussed in class
Britain, USA, Russia
what is the mechanism called which allows multiple devices to decide which one gets to use the bus, and when?
Bus arbitration
What is a bus device which is passive and must wait for a bus request before it can "talk?"
Bus slave
A ________ machine is a computer that has a relatively large number of complex instructions
CISC
CMOS or TTL: Which technology takes longer to switch states
CMOS
CMOS or TTL: which takes up less space
CMOS
The USB data payload add a [a] to the end of each packet which allows the receiver to know if that data is valid or not.
CRC
WHats wrong/ deceptive about calling RAM. "RAM?"
Calling RAM "RAM" is deceptive because RAM is actually not randomly accessed. There is actually a certain way to obtain memory
What is the name of the area of memory in the IJVM which holds constants?
Constant Pool
. Which areas of memory below are loaded by the word (32 bits at a time)?
Constant Pool Local Variable Frame Operand Stack
A _________ chip is a peripheral chip we discussed which can be used by a CPU to count the number of pulses from an external signal.
Counter/ Timer
A __________ chip is a peripheral chip we discussed which is used to take a binary number from a CPU and convert it to an equivalent voltage value.
DAC
Which is the fastest memory technology listed ?
DDR SDRAM
What makes DDR SDRAM "double data rate"
DDR SDRAM achieves "Double data rate" by transferring data on both the rising and falling edges of the computer's clock signal
Which memory technology has RAS and CAS lines
DRAM
Which of the following is not considered a subset of the control pins of a typical CPU
Data
For the timing diagram of the IJVM data cycle below, what happens at time 5
Data propagates from shifter to registers
What was "Level 0" for the six-level computer as discussed in class?
Digital Logic Level
For the timing diagram of the IJVM data cycle below, what happens at time 3
Drive Hand B bus
Which memory technology is FLASH memory most closely related
EEPROM
Which memory technology is used for storing non-volatile data and can be read from and written to one byte at a time?
EEPROM
Which memory technologies have aa "windoe" in them ?
EPROM
Which memory technologies need a label on it after being programmed
EPROM
What is the major advantage of using an EPROM instead of a Masked Part?
EPROM can be erased and reprogrammed, but a Masked Part is unchangeable once programmed
What is the major advantage of using an EPROM instead of a Masked Part?
EPROM is programmed by the user; masked ROM is programmed during manufacturing
Why is the word "embedded" used in the term embedded computer? What does it mean?
Embedded is used because it is still part of the computer as a whole. It does specific tasks assigned, allowing other parts of the computer to execute faster
What does EPROM stand for?
Erasable Programmable Read Only Memory
What does EDO in EDO DRAM stand for
Extended Data Output
WHat does FPM in FPM DRAM stand for?
Fast Page Mode
What three things does a computer do over and over?
Fetch, decode, execute
Which memory technologies would be the best choice for storing code in an embedded system which is under development
Flash EEPROM EPROM
Give an advantage of using Flash over EEPROM
Flash is smaller and faster and can be reprogrammed up to a million times
What is an asynchronous bus cycle called which has the following sequence of events? 1. MSYN# is asserted 2. SSYN# is asserted 3. MSYN# is deasserted 4. SSYN# is deasserted
Full handshake
Which ISA level IJVM instruction does an unconditional branch?
GOTO
Who stated that the amount of transistors engineers can put on a piece of silicon will double every eighteen months?
Gordon Moore
What was "Level 6" for the six-level computer as discussed in class?
Graphical Programming Environment
In what sense are hardware and software equivalent?
Hardware and software are equivalent because without them the computer or machine would not work. As an example, hardware is like the human body while software is like the brain. Without the human body such as legs and arms, the body would not be able to complete the task that the brain wants it to do; however, without the brain, the human body would not be able to move. This is the same when referring to hardware and software.
Besides an early steam engine, who created an automatic scene changer for plays 2000 years ago?
Heron of Alexandria
What is the purpose/function of the H register in the IJVM architecture?
Holds the data that is to be supplied A, and is the only register that is able to perform this function
Which ISA level IJVM instruction removes the top two things from the stack, adds them together, and puts their sum on top of the stack?
IADD
Which ISA level IJVM instruction removes the top two things from the stack, does a bitwise AND, and puts the result on top of the stack?
IAND
What bus did the ISA originate from?
IBM PC BUS
WHat bus did the ISA originate from
IBM PC Bus
Which IS level IJVM instruction adds a constant to a local variable?
IINC
Which ISA level IJVM instruction calls a function (method)?
INVOKEVIRTUAL
Which ISA level IJVM instruction returns an integer from from a function (method)?
IRETURN
Why can the architecture of the Omnibus system mentioned in Chapter 1 be potentially faster than that of the Von Neumann architecture?
Input and output is not directly stored into memory when using the Von Neumann system because it must always go through the ALU; however, for the Omnibus system, input and output can go directly to the memory.
What was "Level 2" for the six-level computer as discussed in class?
Instruction Set Architecture level
What defines the "Third generation of computing?
Integrate circuit
Translated code or Interpreted: Which takes less time to produce the first executable instruction?
Interpreted code
Give the major advantage of using EEPROM instead of EPROM
It is erasable using electrical signals instead of light the main use is where is where reprogramming and non-volatility are important
What is the purpose/function of the TOS register in the IJVM architecture?
It is the top of stack register where it holds the data value at the top of the stack.
What is the primary advantage of adding a microprocessor or microcontroller to a system which does not already contain a processor?
It will make the system faster, typically by allowing input and output to move from and to memory without going through an ALU.
How is ROM better than RAM ?
Its contents are retained when the power is cut off. It is non-volatile and doesn't loose its contents easily
Give an example of a multi-level computer in which the device level and the digital logic level are not the lowest level.
Java Virtual Machine
What is the name of the pointer which points to the area of memory in the IJVM which holds a function's (method's) parameters?
LV
All IJVM instructions fetched from memory come into what register(s)?
MBR
All data in the IJVM architecture placed on the memory data bus comes from what register?
MDR
Which register(s) in the IJVM architecture can be put on the B BUS?
MDR, OPC, SP, MBR, PC, LV, CPP, TOS
Which register(s) in the IJVM architecture is/are used to store the current microinstruction being executed?
MIR
Whch memory technology would be the best for storing code in an embedded system which will be in every automobile made next year?
Masked ROM
Which memory technologies cannot be programmed (written to) by the user
Masked ROM
Which memory technology would cost the least if you purchase a million of them
Masked ROM
Which memory technology would cost the most, if you purchase only one?
Masked ROM
What is the purpose/function of the MAR register in the IJVM architecture?
Memory Address Register: Contains word address and stores them in MDR
What is the name of the area of memory in IJVM where instructions are stored?
Method Area
What was "Level 1" for the six-level computer as discussed in class?
Microarchitecture Level
Which are advantages hardware has over software?
More robust and faster
Which of the following bus terms could be employed to help minimize the physical size of a CPU?
Multiplexed bit
Which of the following bus terms could be employed to help minimize the physical size of a CPU?
Multiplexed bus
Which ISA level IJVM instruction does no operation, but simply delays a microinstruction?
NOP
WHat is a battery-backed-up SRAM called?
NVRAM
Which memory technologies are nonvolatile?
NVRAM EPROM Masked ROM Flash EEPROM OTP, PROM
For the timing diagram of the IJVM data cycle below, what happens at time 7
New MPC value available
For the timing diagram of the IJVM data cycle below, what happens at time 1?
New MPC value used to load new MIR value here
Is it possible for a computer to compile code directly to the microarchitecture level instead of the ISA level? Why or why not?
No. The computer needs to go through the ISA level to know what it is assembling
Which memory technologies cannot be programmed in-circuit ?
OTP EPROM Masked ROM
Which memory technology blows fuses within it to store its data
OTP, PROM
Which memory technologies would you typically use to store code in your embedded computer?
OTP, PROM EPROM masked ROM Flash
What does OTP stand for?
One time programmable
For the timing diagram of the IJVM data cycle below, what happens at time 4
Operate ALU and Shifter
What was "Level 3" for the six-level computer as discussed in class?
Operating system Machine level
What is the name of the pointer which points to the area of memory in the IJVM where instructions are stored?
PC
Which register(s) in the IJVM architecture is/are 32-bits wide?
PC, MDR, CPP, LV, H, OPC, TOS, MAR, SP
Which bus protocol provides the fastest data rate?
PCI
What bus is a successor to the PCI bus which is more like a network of serial data lines?
PCI Express
A ________ chip is a peripheral chip we discussed which can be used by a CPU to expand its I/O capability
PIO
Which memory technology would probably be used to store code in an embedded system which is thought to be bug free and is used test in the field in ten units?
PROM
Which peripheral IC would be best for varying the intensity of an LED?
PWM
A _________ chip is a peripheral chip we discussed which could be used by a CPU to generate various speeds of a motor.
PWM or DAC
The USB has [a] power which means the devices attached to it can get their power from the root hub.
Parasitic
Which computational creation comes closest to our definition of a computer?
Pianola (Player Piano)
______ I/O addressing treats devices as if they were an extension of the register set of a processor.
Port-Based I/O
What was "Level 5" for the six-level computer as discussed in class?
Problem-oriennted language learning
GIVE a huge advantage of EEPROM over an OTP
Proggramming once is not very helpful. OTP is one time programmable, EEPROM can be reprogrammed
What does PROM stand for ?
Programmable Read only memory
How is RAM better than ROM?
ROM cannot be written to or modified as much, as easily or as quickly when compared to RAM
A ____ chip is a peripheral chip we discussed which can be used by a CPU to store the calendar date and time.
RTC
A _________ chip is a peripheral chip we discussed which is routinely integrated with NVRAM.
RTC
A _________ chip is a peripheral chip we discussed which necessarily needs a battery with it.
RTC
Why are registers useful in the memory hierarchy of a computer? That is, why don't we just use the SDRAMs of main memory?
SDRAMs take time to access data while registers already hold the data which makes them faster.
Which ISA level IJVM instruction takes the top two things from the stack and reverses their positions?
SP
Which register(s) in the IJVM architecture point(s) to a location in a stack?
SP, LV
Which memory technologie do not need to be refreshed
SRAM DRAM FPM EDO
Which ISA level IJVM instruction takes the top two things from the stack and reverses their positions?
SWAP
What is an embedded computer?
Self-contained computer devices that have their own programming. They don't have to be controlled by a user or other systems
What does the following C statement do? if ((mask & 0xF0) != 0) g = 2;
Set g if at least one of the four upper bits of mask are set.
What does the following C statement do? if ((mask & 0xF0) == 0xF0) g = 2;
Sets g if all four upper bits of mask are set
For the timing diagram of the IJVM data cycle below, what happens at time 2
Setup Signal to Data Path
What does "S" in SDRAM stand for ?
Synchronous
CMOS or TTL: which is faster
TTL
CMOS or TTL: which requires more power
TTL
Discuss the future of Moore's Law
The future of Moore's Law is that the law is collapsing and will not also be able to work. By his definition, transistors would eventually have to operate on an atomic level which is not possible. This law is not indefinitely sustainable.
What is the memory hierarchy of a computer?
The memory hierarchy of a computer distinguishes each level in the hierarchy by response time. The memory hierarchy is used in computer architecture when discussing performance issues in computer architectural design, algorithm predictions, and the lower level programming constructs such as involving locality of reference. If the triangle of hierarchy starts off with the point at the top then the hierarchy is: Register, Cache, Main memory or RAM, Hard Disk, and then Magnetic Tape.
According to Moore's Law, what will double every eighteen months?
The number of transistors that can be put on a piece of silicon
Does a "pianola" playing piano meet our definition of a computer? Why or why not?
The pianola does not meet our definition of a computer. It is extremely close to doing so though. It is able to execute a set of instructions but has to be hand cranked by the user, so the user is "doing the work"
what do "fat" arrows on a chip schematic signify
They represent more than one signal line, such as for a bus
Every processor IC is made up of many Boolean gates. What are the gates primarily made up of?
Transistors
Why are modern computers created with transistors instead of some other technology
Transistors are faster and cheaper
Translated code or Interpreted: Which takes more time to produce the first executable instruction?
Translated code
A [a] chip is a peripheral chip we discussed which could be used by a master CPU to communicate with a slave CPU
UART
A ________chip is a peripheral chip we discussed which could be used by a CPU in an embedded system to communicate serially to another device.
USART/UARTs
What defines the "First generation" of computing?
Vacuum Tubes
The Java [a] [b] is a "hypothetical computer" that is exactually simulated on computers today allowing different architectures to execute the same exact instructions transmitted on the internet.
Virtual
What is a hypothetical computer, machine Mn , whose 'machine language' is Ln (i.e. greater than L0) called?
Virtual Machine
What are parts of the Von Neumann Machine Diagram?
a. Memory b. Input c. Arithmetic Logic Unit d. Output e. Control Unit
In general, which are advantages of having a relatively large cell size?
a. The computer can access memory faster. b. The computer can access more memory with fewer address lines. c. Accessing integers is simpler
Add circuit pictures 3-2
add
What does ADC stand for?
analog to digital converter
What does "ALU" stand for i
arithmetic logic unit
What type of bus protocol does not use a master clock, but uses aperiodic timing signals instead
asynchronous
The USB bus has four types of frames. One is the ______ frame which is used to transfer large amounts of data from one device to another.
bulk
What is "a common electrical pathway between multiple devices" called?
bus
What is an "integral number of clock cycles" called in which all bus activities take place?
bus cycle
What is the name for memory that's larger than the register set and faster than main memory
cache
What is the name of the pointer which points to the area of memory in the IJVM that holds constants?
constant pool pointer
The USB bus has four types of frames. One is the ________ frame which is used to configure or set up a device
control
Which I/O peripheral chip that we discussed could be used to count the number of rotations of drive shaft?
counter
What is a type of centralized bus arbitration which decides who gets the bus by the order each device is connected on the bus? (i.e. Each device is connected in series and when the arbiter grants usage of the bus, the first device takes it if it requested it. If not, it passes the grant through to the next device, etc...)
daisy chain
A computer's program memory can be divided into two types. The type which holds variables to be operated on and which is written to as much as read from is called what? (i.e. it holds declarations such as: int i)
data
What is the name of the (loop) structure in the CPU that carries out an instruction?
data path
Considering the seven execution steps mentioned in class, what is the fourth step?
decode address if needed
Considering the seven execution steps mentioned in class, what is the third step?
decode type of instruction
What does DAC stand for?
digital to analog converter
WHat does DDR in DDR SDRAM stand for
double data rate
What is a chip called which sits on a bus in order to prevent a master device's signals from having to supply the necessary current to other bus devices.
driver
. Considering the seven execution steps mentioned in class, what is the sixth step?
execute the instruction
Considering the seven execution steps mentioned in class, what is the first step?
fetch instruction
Considering the seven execution steps mentioned in class, what is the fifth step?
fetch memory data is needed
Which generation of computing was characterized by the creation of Very Large-Scale Integrated Circuits?
fourth
Considering the seven execution steps mentioned in class, what is the seventh step?
goto step 1
What is an advantage of interpretation over translation?
i. Begins executing faster ii. Requires less memory
What is an advantage of translation over interpretation?
i. Can find syntax errors in all instructions before executing ii. Allows for optimization of code iii. Executes faster
Considering the seven execution steps mentioned in class, what is the second step?
increment program counter
Who created the PCI bus?
intel
Translated code or Interpreted: Translated code or Interpreted:
interpretation
The USB bus has four types of frames. One is the _________ frame which actually employs polling to allow a device to quickly communicate with the hub.
interrupt
What is a name for the code called which is executed when a certain interrupt is detected?
interrupt Routine
What is the name of a chip which monitors interrupts from multiple devices and then passes on one of the interrupt requests to the CPU?
interrupt controller
What is the table in memory called which stores the interrupt vectors for the various interrupts handled by a CPU?
interrupt vector table
The USB bus has four types of frames. One is the _______ frame which is used for real-time devices such as microphones or speakers.
isochronous
Definition of computer
kasldjf
Pictures for mem-tech questions 3-3
kjlkhkhl
What level of the computer does Chapter 3 primarily deal with
level 0
What is the name of the area of memory in the IJVM which holds a function's (method's) parameters?
local variable frame
) [a] I/O addressing is a bus-based address system in which there is some distinction between I/O and memory using extra signals.
memory mapped
What type of bus has multiple functions on the same lines (e.g. a bus which has addresses and data on the same lines at different times.)
multiplexed bus
Look over parallel structures 2-1
nsklkf
What is the name of the area of memory in the IJVM where operations/calculations are performed?
operand Stack
What does PIO (as in a PIO peripheral chip) stand for?
parallel Input Output
What C type is used to reference dynamically allocated memory?
pointers
What does RTC (as in an RTC peripheral chip) stand for?
real time clock
Most slave devices are connected to a bus by a chip which acts as an amplifier to supply current to the slave devices. These chips are called what?
receiver
For the timing diagram of the IJVM data cycle below, what happens at time 6
register loads instantaneously from C bus and memory
Which generation of computing was characterized by the introduction of the transistor
second
What category of CPU would a processor which performs MPEG decompression for a video receiver fall into?
single purpose
A problem arising from signals on a bus arriving at a location at different times is called what?
skew
) [a] I/O addressing is a bus-based address system in which there is some distinction between I/O and memory using extra signals.
standard
what is a watchdog used for?
to check to see whether supply voltage of the processor is adequate to run properly and whether or not the computer has entered a infinite loop
What is a Bus chip called which acts as both a receiver and driver?
transceiver
What is a bus chip called which acts as both a receiver and driver?
transceiver
According to Moore's Law, what will be able to double on a piece of silicon every eighteen months?
transistors
Translated code or Interpreted: Which executes faster at run-time?
translated code
What are these examples of (translation or interpretation) : i. Compiling a C program ii. Assembling assembly code
translation
More than more register in the IJVM architecture can be loaded from the C bus at one time
true
What does USART stand for?
universal synchronous asynchronous receiver transmitter
I have asked a student to help me fill out 100 identical forms. I tell him what to write in the first blank and he write it down on the first form, then the second, etc... Then I tell him what to write on the second blank, and he fills that out on the first form, then the second, etc... This is repeated until all 100 forms are complete. What type of computer is most analogous to this process?
vector processor
What was the AGP bus used for? (one word)
video
A _________ chip is a peripheral chip we discussed which can be used by a CPU to reset itself if it enters an infinite loop.
watchdog