eet121sima 1/16

VDB normally operates in the

active region

the Q point of a VDB circuit is

almost totally insensitive to changes in current gain

suppose the base resistor is open .the Q point will be

at the lower end of the load line

if the current gain is unknown in an emitter-biased circuit, you cannot calculate the

base current

the current gain of a transistor is defined as the ratio of the collector current to the

base current

for emitter bias,the voltage at emitter is 0.7V less than the

base voltage

For maximum Vce, where should the Q-point be placed?

centered on the load line

the Q point of TSEB does not depend on the

current gain

the collector voltage of a VDB circuit is not sensitive to changes in the

current gain

if the emitter resistance decreases with TSEB, the collector voltage will

decrease

with VDB and increase in collector resistance will

decrease the collector voltage

as the temp increases the current gain

decreases,increases, stays the same

when the collector current increases what does the current gain do?

decreases,stays the same increases

if the base resistor has zero resistance the transistor will probably be

destroyed

if the emitter resistance is reduced by one-half in a VDB circuit, the collector current will

double

if a transistor operates at the middle of the load line ,a decrease in the current gain will move the Q point

down

if the emitter resistance doubles with TSEB, the collector current will

drop in half

VDB has a stable Q point like

emitter bias

a circuit with a fixed emitter current is called

emitter bias

which is the largest current in a pop transistor

emitter current

the first step in analyzing emitter-based circuits is to find the

emitter voltage

if a splash of solder shorts the collector resistor of TSEB, the collector voltage will

equal the collector supply voltage

if the base resistor opens with TSEB, the collector voltage will

equal the collector supply voltage

for the emitter bias,the voltage across the emitter resistor is the same as the voltage between the emitter and the

ground

if the emitter resistor is open, the collector voltage is

high

when there is no base current in a transistor switch , the output voltage from the transistor is

high

the majority carriers in the emitter of a PNP transistor are

holes

if the collector resistor opens in a base biased circuit, the load line will become

horizontal

if the collector resistance decreases in a VDB circuit , the collector voltage will

increase

when the base resistor increases the collector voltage will probably

increase

the major advantage of a photo-transistor as compared to a photodiode is its

increased sensitivity

if the emitter resistance increases,the collector voltage

increases

when the Q point moves along the load line ,Vce decreases when the collector current

increases

with voltage -divider bias , the base voltage is

less than the base supply voltage

if the collector resistor is open the collector voltage is

low

three different q points are shown on a load line . the upper Q point represents the

maximum current gain

the base voltage of two supply emitter bias (TSEB) is

near 0 volt

if the base supply voltage is disconnected the collector emitter voltage will equal

off the load line

VDB needs

only one supply

the currents of a pnp transistor are

opposite npn current

what DMM polarity connection is needed on an npn transistors base to get a 0.7V reading

positive

if the emitter resistance decreases, the

q point moves up

when the current gain increases from 50 to 300 in an emitter biased circuit,the collector current

remains almost the same

with pnp volt-divider bias you must be

resistors

At what point on the load line does saturation occur? At what point does cutoff occur?

sat occurs at intersection of the load line and the Y axis cutoff occurs at the intersection of the load line and the IB=0 curve

if the base resistance is very small the transistor will operate in the

saturation region

in TSEB the base current must be

small

VDB is noted for its

stable Q point

Define Q-point.

the Q-point is the dc point at which a transistor is biased and is specified by VCE and IC

with a TSEB pnp circuit using a negative Vcc supply, the emitter voltage is

0.7 higher than base voltage

the collector current is 1.5mA. if the current gain is 50, the base current is

30uA

the base current is 50A, if the current gain is 100, the collector current is closest in value to

5mA

the current gain of a pnp transistor is

the ratio of collector current to base current

when testing an npn transistor using an ohmmeter , the collector -emitter resistance will be low when

the transistor is defective

What are the upper and lower limits on a dc load line in terms of VCE and IC?

the upper load line limit is IC(SAT) and VCE(sat). the lower limit is IC=0 and VCE(cutoff)

when using a DMM to test a transistor , an approximate reading of 0.7 will be found with how many polarity connections

two

if a transistor operates at the middle of the load line, a decrease in the base resistance will move the q point

up

if the base supply voltage increases, the Q point moves

up

the graph of current gain verses collector current indicates that current gain

varies slightly

ignoring the bulk resistance of the collector diode , the collector emitter saturation voltage is

zero 0