Module 2 Section 3.1 to 3.6

Store instructions: 1) If X22 has 1000, what address does this instruction compute?STUR X9, [X22, #40] 2) If X22 has 1000, X9 has 77, and memory locations 1000, 1008, and 1016 have 10, 15, 20 respectively, what do those locations have after the following instruction?STUR X9, [X22, #8]Type answer as: 10, 15, 20

1040 [X22, #40] computes 40 + (the value in X22), so 40 + 1000, or 1040. 10, 77, 20 [X22, #8] computes address 8 + 1000, or 1008. X9's value of 77 is stored there; other words are unchanged.

What is the largest base ten number representable in 4 bits (assuming the "natural" representation)?

1111two is 15ten. The number can also be computed as 24 - 1.

What is the largest base ten number representable in 8 bits (assuming the "natural" representation)?

255 28 - 1 is 255. That largest number in base two is 11111111two.

What is the largest base ten number approximately representable by 32 bits (assuming the "natural" representation)? 4 million 4 billion 4 trillion

2^32 - 1 is 4,294,967,295, or just over 4 billion.

How is the largest base ten number representable by 64 bits calculated (assuming the "natural" representation)? 2^63 - 1 2^64 2^64-1

2^64 - 1 is approximately 18.5 quintillion.

sign and magnitude representation

is a signed number representation where a single bit is used to represent the sign, and the remaining bits represent the magnitude.

The purpose of a signed load is to ____________________________________________- Unsigned loads simply fill with _______ to the left of the data, since the number represented by the bit pattern is unsigned.

place a correct representation of the number within that register. 0s

In the instruction below, a, b, and c are operands. In such an arithmetic instruction, each operand comes from special hardware called a _____. ADD a, b, c

register Registers can be thought of as the bricks of computer construction.

The function of a signed load is to copy the sign repeatedly to fill the rest of the register, known as a ___________________

sign extension

More registers may benefit an assembly program, but may directly lead to a _____ clock frequency. Type: slower, faster, broken.

slower More registers may mean the clock frequency must be slowed to ensure the clock signal has time to reach every register, thus slowing every instruction. Hence the principle of "Smaller is faster." Of course, too few registers may mean many more instructions must execute, which is slower, so hardware designers seek a good balance.

With more registers, the clock signal requires more time to reach every register, so the clock frequency must be slower.

True

Given the following 64-bit number, what is the most significant bit's value?1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 0

1

Assume X22 has 5000, and doublewords addressed 5000..5002 have the data shown:5000: 995001: 775002: 323 1) What address will be computed by:LDUR X9, [X22, #2] 2) What value will be put in X9 by:LDUR X9, [X22, #0] 3) What value will be put in X10 by:LDUR X10, [X22, #2] 4) Assume X21 has 5001. What value will be put in X11 by:LDUR X11, [X21, #1]

1) 5002 [X22, #2] computes the address as 2 + (the value in X22), so 2 + 5000, or 5002. 2) 99 [X22, #0] will compute the address 0 + 5000, or 5000. The value in the doubleword at address 5000 is 99. Thus, 99 will be put in X9. 3) 323 [X22, #2] will compute the address 2 + 5000, or 5002. The value in the doubleword at address 5002 is 323. Thus, 323 will be put in X10. 4) 323 [X21, #1] will compute the address 1 + 5001, or 5002. The value in the word at address 5002 is 323. Thus, 323 will be put in X11.

Of a doubleword's 64 bits, what is the leftmost bit numbered? 64 63

63

In the LEGv8 architecture, each register is _____ bits wide.

64 64 is a common register width in computer architectures. Some architectures for embedded systems use 8 or 16 bits. 64 bits is becoming common in some high-performance architectures like those used in servers.

Data transfer instruction

A command that moves data between memory and registers.

Instruction format

A form of representation of an instruction composed of fields of binary numbers.

Doubleword

A natural unit of access in a computer, usually a group of 32 bits.

word

A natural unit of access in a computer, usually a group of 32 bits.

Biased notation

A notation that represents the most negative value by 00 ... 000two and the most positive value by 11 ... 11two, with 0 typically having the value 10 ... 00two, thereby biasing the number such that the number plus the bias has a non-negative representation.

One's complement:

A notation that represents the most negative value by 10 ... 000two and the most positive value by 01 ... 11two, leaving an equal number of negatives and positives but ending up with two zeros, one positive (00 ... 00two) and one negative (11 ... 11two). The term is also used to mean the inversion of every bit in a pattern: 0 to 1 and 1 to 0.

Alignment restriction:

A requirement that data be aligned in memory on natural boundaries.

two's complement representation:

A signed number representation where a leading 0 indicates a positive number and a leading 1 indicates a negative number. The complement of a value is obtained by complementing each bit (0 → 1 or 1 → 0), and then adding one to the result (explained further below).

Address

A value used to delineate the location of a specific data element within a memory array.

For hardware and software interface...

As the addresses in loads and stores are binary numbers, we can see why the DRAM for main memory comes in binary sizes rather than in decimal sizes. That is, in gibibytes (230) or tebibytes (240), not in gigabytes (109) or terabytes (1012).

Machine language:

Binary representation used for communication within a computer system

overflow

If the number that is the proper result of such operations cannot be represented by these rightmost hardware bits, overflow is said to have occurred.

Elaboration...

In many architectures, words must start at addresses that are multiples of 4 and doublewords must start at addresses that are multiples of 8. This requirement is called an alignment restriction. (COD Chapter 4 (The Processor) suggests why alignment leads to faster data transfers.) ARMv8 and Intel x86 do not have alignment restrictions, but ARMv7 and MIPS do.

Elaboration:

It is not quite true that ARMv8 has no alignment restrictions. While it does support unaligned access to normal memory for most data transfer instructions, stack accesses and instruction fetches do have alignment restrictions.

Elaboration

Let's put the energy and performance of registers versus memory into perspective. Assuming 64-bit data, registers are roughly 200 times faster (0.25 vs. 50 nanoseconds) and are 10,000 times more energy efficient (0.1 vs 1000 picoJoules) than DRAM in 2015. These large differences led to caches, which reduce the performance and energy penalties of going to memory (see COD Chapter 5 (Large and Fast: Exploiting Memory Hierarchy)).

If these elements were doublewords, these addresses would be incorrect, since LEGv8 actually uses byte addressing, with each doubleword representing 8 bytes. The animation below (COD Figure 2.3) shows the correct memory addressing for sequential doubleword addresses.

TRUE

When loading a 64-bit doubleword into a 64-bit register, the point is moot; signed and unsigned loads are identical T/F

TRUE

3.5.1: Example of translating a LEGv8 assembly instruction into a machine instruction.

The assembly instruction will be converted to a machine instruction. The machine instruction has 5 fields. The first field (containing 1112) tells the LEGv8 computer that this instruction performs addition. The second field gives the number of the register that is the second source operand (21 for X21), and the fourth field gives the other source operand (20 for X20). The fifth field contains the number of the register that is to receive the sum (9 for X9). The third field is unused in this instruction, so it is set to 0. This instruction can be represented as fields of binary numbers as opposed to decimal.

load.

The data transfer instruction that copies data from memory to a register is traditionally called lodLDUR, standing for load register.

Stored-program concept:

The idea that instructions and data of many types can be stored in memory as numbers and thus be easy to change, leading to the stored-program computer.

store and load

The instruction complementary to load is traditionally called store; it copies data from a register to memory. The format of a store is similar to that of a load: the name of the operation, followed by the register to be stored, then the base register, and finally the offset to select the array element. Once again, the LEGv8 address is specified in part by a constant and in part by the contents of a register. The actual LEGv8 name is STUR, standing for store register.

Most significant bit:

The leftmost bit in an LEGv8 doubleword.

Least significant bit:

The rightmost bit in an LEGv8 doubleword.

Instruction set

The vocabulary of commands understood by a given architecture.

What is 2s complement based on?

This shortcut is based on the observation that the sum of a number and its inverted representation must be 111 ... 111two, which represents −1. Since x + x̄ = −1, therefore x + x̄ + 1 = 0 or x̄ + 1 = −x. (We use the notation x̄ to mean invert every bit in x from 0 to 1 and vice versa.)

The LEGv8 assembly language notationADD a, b, cinstructs a computer to add the two variables b and c and to put their sum in a.

True

The clock signal requires time to reach every register.

True

Thus, registers take less time to access and have higher throughput than memory, making data in registers both considerably faster to access and simpler to use. Accessing registers also uses much less energy than accessing memory. To achieve the highest performance and conserve energy, an instruction set architecture must have enough registers, and compilers must use registers efficiently.

True

True or False

Two's complement does have one negative number that has no corresponding positive number: −9,223,372,036,854,775,808ten. Such imbalance was also a worry to the inattentive programmer, but sign and magnitude had problems for both the programmer and the hardware designer. Consequently, every computer today uses two's complement binary representations for signed numbers.

Decimal proved so inefficient that subsequent computers reverted to all binary, converting to base 10 only for the relatively infrequent input/output events

Why binary vs decimal

sign and magnitude representation has several shortcomings. Do these all apply? 1. not obvious where to put the sign bit 2. adders for sign and magnitude may need an extra step to set the sign because we can't know in advance what the proper sign will be. a separate sign bit means that sign and magnitude has both a positive and a negative zero, Because of these shortcomings, sign and magnitude representation was soon abandoned.

Yes True

ADDI X22, X22, #4 // X22 = X22 + 4 Constant operands occur frequently, and by including constants inside arithmetic instructions, operations are much faster and use less energy than if constants were loaded from memory.

before: LDUR X9, [X20, AddrConstant4] // X9 = constant 4 ADD X22, X22, X9 // X22 = X22 + X9 (X9 == 4)

The below animation shows the conversion of an assembly instruction into a machine instruction consisting of 0's and 1's. A machine instruction is composed of ______________, each ____________having several bits and representing some part of the instruction.

fields, field