OT Micro Exit 1
mm = __ is automatically used for direct addressing
00
Given a synchronous sequential circuit what is the next state with input = 1, if the current state is 001?
010
If an ASCII of A is used with even parity the results is
0100 0001
10110 - 01101 using 1's complement
01001
A parity bit is used in error detecting codes, if an ASCII of T is used with odd parity the result is
0101 0100
3. The adjacency matrix of the graph is seen below, determine how many edges are in the graph. 121 200 022
10
Given a synchronous sequential circuit what is the next state with input = 0, if the current state is 010?
100
Using 2's complement, what is the binary equivalent of -7?
1001
The 2's complement representing the value -12 is
10100
If an ASCII of A is used with odd parity, the results is
1100 0001
The 2-4-2-1 code of 7
1101
SHLD AX, BX, 4 AX = 1234h BX = 5678h
2345h
How many base theorems and postulates to prove x + xy = x
3
The graph is represented by the adjacency matrix below. Determine the out-degree in vertex d 0230 1221 2110 1002
3
How many 4-binary adders are needed to create a single digit binary adder?
4
4-bit magnitude comparator combinational circuit A = B what logic gate?
4-input AND gate
4-bit magnitude comparator combinational circuit A < B what logic gate?
4-input OR gate
8088 I/O ad space, number of I/O ports?
4096
Decimal parallel adder that adds 5 decimal digits requires how many BCD adder stages?
5
Determine in-degree in vertex b? Matrix: a b c d a 0 2 3 0 b 1 2 2 1 c 2 1 1 0 d 1 0 0 2
5
How many additional control reg are activated based from Pentium's protected mode
5
30. The execution time for an alu instruction going from memory to immediate requires how many clock cycles?
5 clock cycles
Give the adjacency matrix of the graph G {a,b,c,d}, How many number of paths from a to d has a length exactly equal to 4? 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0
8
The binary value 0111 represent a decimal value of 1 in this decimal code
8 4 -2 -1
Machine code for SAHF
9E
Machine code for LAHF
9F
20. In stack memory addressing, whenever the data are popped from the stack, which bits are removed from the location addressed by SP? a. Low-order 8-bits b. No bits are removed from SP but rather on BP c. None of the choices d. Both low-order and high-order 8-bits e. High-order 8-bits f. 16 bits from BP are removed
A
24. What circuit technology is preferable in systems requiring low power consumption? a. CMOS b. TTL c. None of the choices d. RTL
A
32. What flag register is not affected by the arithmetic operation ADD? a. Trap Flag b. Sign Flag c. Parity Flag d. Zero Flag
A
42. Using the signed-2's complement format, the representation of -7 is __________. a. 1001 b. 1111 c. 1000 d. 1100
A
A 2 bit by 2 bit multiplier is simply implemented using which of the following combinational circuit? A. 2 Half Adders and 4 AND gates B. 2 Full Adders and an OR gate C. 2 Full Adders and 4 AND gates D. One 4 bit binary adder, 2 AND gates and 1 OR gate
A
A decimal parallel adder that adds 5 decimal digits requires how many BCD adder stages. A. 5 B. 6 C. 3 D. 4
A
A parity bit is used in error detecting codes, if an ASCII of A is used with odd parity the result is A. 1100 0001 B. 0101 0100 C. 0100 0001 D. 1101 0100
A
ARM stands for A. Advance RISC Machines B. Advance Response Machines C. Advance RISC Model D. Advance Reprogrammable Model
A
Determine the canonical form of the simplified Boolean expression F=x'y'z' + xz a. m (0,5,7) b. m (2,4,7) c. m (0,2,3,7) d. m (1,6,7)
A
Determine which of the given relations on the set of all integers is an antisymmetric relation where (x, y) is an element of R. x is greater than or equal to y2 x is a multiple of y xy is greater than or equal to 1 x is not equal to y
A
Express the following function as a sum of minterms: (xy + z)(y + xz) x'yz + xy'z + xyz' + xyz x'y'z + xy'z + xyz x'yz + x'y'z + xyz'+ xyz x'y'z + xyz' + x'y'z
A
Memory of 8 bit? Choices: [A 16kB, B 8kB, C 64kB]
A
Reduce the Boolean expression W'X(Z' + Y'Z) + X(W + W'YZ) to 1 literal A. X B. W C. Z D. Y
A
Set A = {integer numbers}, which is antisymmetric a. R = {(a,b) | a > b} b. R = {(a,b) | a + b = 3} c. R = {(a,b) | a - b = -4} d. R = {(a,b) | a = b or a = -b}
A
Simplify the Boolean function to a minimum number of literals A B C T1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 A'(B' + C) A + BC A'B + C ABC + A'B'C'
A
Simplify the Boolean function to a minimum number of literals. A B C T2 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 A + BC ABC + A'B'C' A'(B' + C') AB + C
A
Suppose the universe of discourse of the propositional function P(x, y) consists of pairs x and y, where x is (1, 2, 3) and y is (1, 2, 3). Represent the proposition ∀y P(1, y). P(1,1) ˄ P(1,2) ˄ P(1,3) P(1,1) v P(1,2) v P(1,3) P(1,1) ˄ P(1,2) v P(2,3) P(1,1) v P(2,2) v P(3,3) P(1,1) v P(2,1) v P(3,1) P(1,1) ˄ P(2,1) ˄ P(3,1)
A
The ____ part specifies the addressing mode for the selected instruction a. MOD b. Addr-low c. REG d. R/M
A
The following is true for r/m except for A. r/m are used for addressing modes B. r/m refers to registers enclosed in brackets C. when mod = 11, r/m indicates a register field D. r/m specifies the addressing mode
A
The lower byte of the flag register contains 83h. What is the result of an LAHF instruction? A. AH = 83h B. AX = 83h C. AL = 83h D. all the flags are set to 83h
A
The lower byte of the flag register contains 83h. Which flag registers are cleared as a result of executing LAHF instruction? A. PF B. SF C. none of the choices D. CF
A
What gate comes before/after the decoder in a majority voting circuit? Choices: [A AND, B OR, C XOR gate]
A
What segment is used for store destination string? a. ES b. Any c. DS d. CS
A
Which of the following cannot be found in microprocessor/ microcontroller/ CPU Choices: A Memory, B ALU, C Register
A
Which of the following is a bit manipulation instruction? A. any of the choices B. NOT AL C. SHL DL, 2 D. ROL AX, 1
A
Which of the following is a logical instruction? A. TEST B. ADC C. SHL D. CMP
A
fast retrieval? Choices: A Static RAM, B Dynamic RAM, C ROM, D NVRAM
A
33. What registers are affected by the arithmetic operation, XOR AH, FFH a. SF b. TF c. DF d. PF
A and D
This input is used to force the Pentium to limit addressable memory to 1 Mb to emulate the memory space of the 8086.
A20M
The higher byte of the flag register contains 83h. Which flag registers are cleared as a result of executing LAHF instruction?
AF
15. If both inputs of a NOR gate is inverted the resulting gate is like the connective _______.
AND
Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
AND gates, OR gates, and NOT gates
Based from order, when PUSHA is applied which register is PUSHED first?
AX
ARM stands for
Advanced RISC Machines
Which of the ff logical operator is performed first?
And
Machine code ROL BYTE PTR[SI],
Answer: final value = 82H → D004 - 1101 0000 0000 0100
What is the highest privilege (RPL) in protected mode?
Answer: 00 *note: 00 - highest 11- lowest
2 bit by 2 bit multiplier can be constructed by using:
Answer: 2 Half Adders and 4 AND gates
4 input (D0-D3) priority encoder circuit contain 3 output (x,y) pertaining to arbitrary values. What is the function for most significant bit y?
Answer: D2 + D3
- convert assembly language into machine code. It takes basic computer instructions and converts them into a pattern of bits that the computer's processor can use to perform basic operations. - convert high level languages (like C, C++) into machine code - computer program which executes a statement directly (at runtime)
Assembler Compiler interpreter
2 to 4 line decoder, made of NAND gates which input would produce an output of 1011 from D0 to D3 1XX 001 011 010
B
28. This specifies the number of loads that output of a gate can drive without comprising its performance a. Output Line b. Fan-out c. None of the choices d. Fan-in e. Input line
B
A 3 x 8 decoder contains output from D0 to D7. Which output is activated high if the input expression x'yz'? A. D1 B. D2 C. D4 D. D5
B
A parity bit is used in error detecting codes, if an ASCII of T is used with odd parity the result is A. 0100 0001 B. 0101 0100 C. 1101 0100 D. 1100 0001
B
Intel's server and workstation powerhouse. Choices: A Celeron B Xeon
B
It is the standard bus connector agreed upon by the PC business comprising of 62 pins found in early PC motherboards that allow expansion with the 8088 microprocessor. A. SATA connector B. ISA connector C. RS232C connector D. SCSI connector
B
Simplify F(v, w, x, y, z) = Σm (0, 1, 2, 4, 5, 8, 9, 10, 12, 16, 17, 18, 20, 21, 24, 26, 29) using Karnaugh map. a. v'w'y' + v'x'z' + vxz + v'y'z' + v'x'y' + vxy'z b. w'y' + x'z' + v'y'z' + v'x'y' + vxy'z c. none of the choices d. vw'y'+ v'x'z' + vxz + v'y'z' + v'x'y' + v'xy'z
B
Simplify the Boolean function F(A,B,C,D) = m(0,2,3,5,7,8,10,11,13,15) B'C + CD + BD B'D' + BD + B'C B'D' + BD + A'C'D A'B'D' + AB'D' + CD
B
Type of RAM that changes during regular interval Choices: [a Static RAM, b Dynamic RAM, c ROM, d NVRAM]
B
Using the signed-2's complement format, the representation of -7 is __________. A. 1111 B. 1001 C. 1100 D. 1000
B
Where will you know if it is in 16 bit or 32 bit? Choices: A. AV, B. D, C. G, D. RPL
B
Which of the ff is a bit manipulation instruction? a. SHL DL, 2 b. Any c. ROL AX,1 d. NOT AL
B
Under precedence of logical operators which is performed last?
Biconditional
14. Determine the bitwise implication of p = 1101011 and q = 1011100 a. 0100011 b. 0010100 c. 1011100 d. 1101011
C
17. Which is false for r/m a. r/m register enclosed in brackets b. r/m used for addressing mode c. r/m specifies addressing mode d. Mode = 11; r/m = register field
C
A 4-input (D0 - D3) priority encoder circuit contain 3 output functions (x, y) pertaining to binary values. What is the function for the least significant bit y? A. D2 + D3 B. D1 + D2 + D3 C. D3 + D1 D2' D. D2 + D1' D3
C
A parity bit is used in error detecting codes, if an ASCII of A is used with even parity the result is A. 1100 0001 B. 1101 0100 C. 0100 0001 D. 0101 0100
C
Determine the canonical form of the simplified Boolean expression F2 = xy'z' + x'y a. m (0,5,7) b. m (2,4,7) c. m (2,3,4) d. m (1,6,7)
C
Express the function below as a standard form product of maxterms. F = xy + x'z (x + y + z)(x + y' + z)(x' + y + z') (x + y + z)(x + y' + z)(x' + y + z) (x' + y)(x + z)(y + z) (x + y + z)(x + y' + z)(x' + y + z)(x' + y + z')
C
If 8088 has frequency of 4MHz, the time of one T state? [200 ns; 80 ns, 250 ns; 300 ns]
C
If a 2 to 4 line decoder is made of NAND gates, which input would produce an output of 1011 from D0 to D3? A. 010 B. 011 C. 001 D. 1xx
C
It is an instruction used to preserve the contents of the outer loop counter. A. LOOP B. PUSH C. PUSH and POP D. POP
C
It is considered as a system signal used in troubleshooting techniques for 8088 hardware architecture. A. DEN B. INTR C. HLDA D. ALE
C
Perform the binary division 1111 0011 ÷ 1001 to obtain the quotient. A. 10101 B. 10111 C. 11011 D. 11101
C
Refer to the behavior of synchronous sequential circuit below. Assume that the states are identified as the combination ABC. What is the complement of the next state for an input of 1, if the current state is 001? A. 010 B. 011 C. 101 D. 110
C
The direction flag is set to 0 using this instruction. A. CLC - clear carry B. CMC - complement carry C. CLD - clear direction flag D. STC - set carry
C
Understand the code Choices: [A Interpreter,B Compiler, C Assembler, D Debugger]
C
What is the canonical form of the simplified function F = C 'D + ABC '+ ABD '+ A 'B 'D a. M (0,1,2,3,5,9,11,12,14) b. M (1,3,4,5,6,7,9,10,12,14,15) c. M (0,2,4,6,7,8,10,11,15) d. M (1,3,5,9,12,13,14)
C
Which of the ff correctly describes the graph Matrix: a b c a 1 0 1 b 0 0 1 c 1 1 1 a. Simple directed graph with 3 vertices b. Pseudograph with 3 vertices c. Directed multigraph with 3 vertices d. Simple multigraph with 3 vertices
C
Direction flag is set to 0 using this instruction.
CLD
Signal that has I/O clk
CLK
Intel introduced cache memory for this microprocessor when it was launched. The Western Design Center, Inc (WDC) introduced this microprocessor in 1982 and was used as the CPU in the Apple IIe and IIc personal computers.
CMOS 8502
Invert carry flag
CMP
Internal high speed memory
Cache
Who made calculator into computer?
Charles Babbage
A U A' = U
Complement Law
What law? P U -P = U
Complement law
34. Intel marketed this microprocessor in April, 1972, and was the basis for the famous "Mark-8" computer kit. a. 8085 b. 8088 c. 8086 d. 8008
D
A product term where in which all the variables appear once, rather complemented or uncomplemented is called __________ A. maxterm B. POS C. SOP D. minterm
D
Based from order, when the instruction PUSHA is applied, which of the following register is "PUSHED" last? A. CX B. AX C. SI D. DI
D
Determine the canonical form of the simplified Boolean expression F = x'y'z + xy a. m (0,5,7) b. m (2,4,7) c. m (2,3,7) d. m (1,6,7)
D
Determine which of the given relations on the set of all integers is an equivalence relation where (x, y) is an element of R. x is a multiple of y x greater than or equal to y2 x = y2 x and y are both negative or both nonnegative
D
Digital integrated circuits are classified not only by their complexity or logical operation, but also by the specific circuit technology to which they belong. The circuit technology is referred to as ____ A. none of the choices B. CMOS family C. TTL family D. digital logic family
D
How many basic theorems and postulates are used to prove the expression x + xy = x A. 6 B. 4 C. 5 D. 3
D
If set A of the universal set U which of the following expression is true? A. ¬A ∩ U = A B. A - U = A C. A ᴜ U = A D. A ⊕ U = ¬A
D
Registers AX, BX and CX contain the following values respectively: 1234h, 5678h and 9ABCh. What is the result of the instruction SHRD BX, CX, 8? A. 9A78h B. 9A56h C. 2345h D. BC56h
D
The 74LS83 is an example of a 4-bit parallel adder. To expand this device to an 8-bit adder, you must A. use four adders with no interconnections B. use two adders and connect the sum outputs of one to the bit inputs of the other C. use eight adders with no interconnections. D. use two adders with the carry output of one connected to the carry input of the other
D
The 8088's I/O addressing space contains how many possible input/output ports? A. 1048576 B. 4096 C. 1024 D. 65536
D
The lower byte of the flag register contains 83h. Which flag registers are set as a result of executing LAHF instruction? A. PF B. ZF C. AF D. SF
D
Which is a valid conclusion? Choices: (a) All hummingbirds are richly colored (b) No large birds live on honey (c) Birds that do not live on honey are dull in color (d) Hummingbirds are small
D
Which of the propositional expression is contradiction? a. (p ^ q)' -> p b. (p -> q)' -> q' c. (p -> q)' -> p d. (p->(p v q))'
D
3x8 decoder D0 to D7 which output is activated high if input x'yz'
D2
4 input (D0-D3) priority encoder circuit contain 3 output (x,y) pertaining to arbitrary values. What is the function for most significant bit x?
D2 + D3
4 input (D0-D3) priority encoder circuit contain 3 output (x,y) pertaining to arbitrary values. What is the function for least significant bit x?
D3 + D1D2'
Based from order, when PUSHA is applied which register is PUSHED last?
DI
11. This processor introduced streaming extensions, with 128-bit registers designed to move large data. a. Pentium 1 b. 80486 c. None of the choices d. Pentium 4 e. Pentium 3 f. Pentium 2
E
Given the undirected graph V = {a,b,c,d,e} with E = {(a,b).(a,d),(b,c),(c,d),(d,e)} is classified as?
Eulerian Path
-visits every edge exactly once and starts and ends on the same vertex - visit every vertex only once
Eulerian circuit Hamiltonian path
29. The flip-flop _________ table provides the value of the next state when the values of the inputs and the present state are known
Excitation table
12. Determine the least number of NAND gate that can be used to implement the expression, (AB + A'B')'(CD' + C'D) a. 12 b. 10 c. 9 d. 13 e. 14 f. 11 g. 8
F
5. How many clock cycles would it take to finish seven instructions in an 8-stage non-pipelined processor? a. 14 b. None of the choices c. 24 d. 54 e. 16 f. 56
F
The complement of F = [x(y'z' + yz)]
F' = x(y+z')(y'+z)
Consider the symbolic logic taken from Lewis Caroll illustrating how quantifiers are used in statements. Which of the following is/are premises? I. All lions are fierce II. Some lions dont drink coffee III. Some fierce creatures do not drink coffee
I and II
System signal used in troubleshooting techniques for 8088 hardware architecture?
INTR
Standard bus connector agreed by PC bus connector agreed upon by the PC business comprising of 62 pins found in early PC motherboards that allow expansion with the 8088 microprocessor
ISA connector
What law: p^p = p or p v p = p p ^ 1 or p v 0 p ^ (pvq) = p or p v (p^q) = p
Idempotent Law identity law absorption law
P^P = P or PvP = P
Idempotent law
First Commercial 8 bit
Intel 8008
10 - 1000 gates in a single package:
LSI
This method of storing 16-bit numbers in memory, wherein the lower byte is already read/write to the lower memory address
Little Endian
F = xy + x'z express as product of maxterms
M(0,2,4,5)
These instructions are used to preserve the contents of the outer loop counter
PUSH and POP
-Pushes all registers to the stack -push data onto stack -Push word onto stack -Push double word onto stack -push all registers to stack (60) Order: AX, CX, DX, BX, SP, BP, SI, DI -Push flags onto stack (9C)
PUSHA PUSH PUSHW PUSHD PUSHA PUSHF
Vertex F
Pendant
An algorithm that uses Selection to solve uses a Big-O notation of
Quadratic
Race condition in R-S Latch
R =1 S=1
INT AX, DX
Read from DX , write to AX
A processor running in this mode can exploit only the lowest 20 bits of its address bus and is therefore limited to the meager 1MB memory space.
Real mode
-is a temporary storage of information inside the CPU. - is a circuit contained in CPU that is used to perform arithmetic and logical operations - is part of the computer that is used to store information permanently or temporarily.
Register ALU Memory
Addressing mode executes its instructions within CPU without the necessity of reference memory for operands?
Register mode
Lower byte of flag reg = 83H. Which flag registers are set as a result of LAHF instruction?
SF
Which of the following is BIT MANIPULATION? Choices: A SHL B OR C AND
SHL
a. _____ - fast, easy interface, small size (16 bytes per chip) b. _____ - high density (256K per chip), requires numerous refreshing cycles to retain data. c._____ - retains memory even power is turned off
STATIC RAM DYAMIC RAM NOTE: Both STATIC and DYNAMIC lose info when turned off NVRAM
Instruction that sets carry flag to 1
STC
If the function v(w+x+y)z would be implemented using NOR gates?
Six NOR gates will be used
Which technique does the Pentium Pro employs where the processor looks ahead into the instruction stream pipeline can be kept busy?
Speculative execution
Which of the following is a logical instruction?
TEST
The expression below is regarded as (p ^ q) -> (p v q)
Tautology
Developed a single general-purpose chip that could be programmed to carry out a calculator's function.
Ted Hoff
is a memory cache that stores recent translations of virtual memory to physical addresses for faster retrieval
Translation Lookaside buffer
74LS83 is an example 4-bit parallel adder to expand to 8-bit you must
Two half adders with the carry output of one connected to the input of the other
Master slave D-flip flop is similar to a synchronous edge triggered flip flop, therefore it should have the ff behavior except?
a change in output is activated by a clock pulse.
Digital integrated circuits are classified not only by their complexity or logical operation, but also by the specific circuit technology to which they belong. The circuit technology is referred to as ____.
digital logic family
INTR
flag ground
Which is used as the medium of communication between the processor and the outside world.
i/o port
An algorithm that uses Hamiltonian cycle to solve uses a Big-O notation of
logarithmic complexity
Product term wherein which all variables appear once rather complement or uncomplemented
minterm
This is the time needed by a gate in processing its input signals before the output signal can be generated
propagation delay time
There exists x not P(x)
there is an x for which P(x) is false
Which of the following relations from Set A = [1,2,3,4] to Set A is considered transitive?
{(1,1),(1,2),(2,1)}
16. What segment register is accessed by the instruction MOV AX, [BP]? a. Stack Segment b. Data Segment c. Extra Segment d. None of the choices e. Code Segment
A
27. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates? a. AND gates, OR gates, and NOT gates b. AND gates and NOT gates c. OR gates and NOT gates d. OR gates only e. AND gates and OR gates
A
36. How many clock cycles would it take to finish seven instructions in an 8-stage non-pipelined processor? a. 56 b. 54 c. None of the choices d. 15
A
37. Which of the following inputs provide a don't care in the output y given by the function F(w, x, y, z) in a BCD to excess-of-3 code converter? a. 1011 b. 1001 c. 0000 d. 0001
A
46. The 4-bit magnitude comparator combinational circuit generates the final output for A = B at what logic gate? a. 4 input AND logic gate b. 4 input OR logic gate c. 4 input XOR logic gate d. 4 input NOR logic gate
A
52. Simplify the Boolean function F(A, B, C, D, E) = ∑(0, 1, 4, 5, 16, 17, 21, 25, 29) a. A'B'D' + AD'E + B'C'D b. B'D'E + CD' + ABC'D c. B'D + A'BD + ABC'E' d. BD + B'DE + A'B'C'
A
What is the result of NEG AX if AX contains FFECh?
Answer: 0014h Machine Code: F7D8h
SHLD AX, BX, 4
Answer: 2345H Machine Code: 0FA4 D804
Result of executing RCL DL, 1; cleared flags; DL contains 93h
Answer: 26h Machine Code: D0D2
Machine code XOR AX, CX
Answer: 31C8 or 0011 0001 1100 1000
ROR AX, 1
Answer: 4FA5H Machine Code: D1C8
Result of executing RCR AX, CL if CL contains 2 and AX contains ABCDh
Answer: AAF3 Machine Code: D3D8
AX, BX, CX = 1234H, 5678H, 9ABCH ; result of SHRD BX, CX, 8?
Answer: BC56 Machine Code: 0FAC CB08
What does the command IN AL, DX mean?
Answer: IN AL, DX : Input byte from I/O port in DX into AL
13. Compute for the number of clock cycles of 9 instructions in a superpipeline system. a. 28 b. 126 c. 180 d. 22 e. None of the choices f. 18
B
18. The content of a 4-bit register is initially 0110. The register is shifted 8 times to the right, with the sequence 10110111 as the serial input. The leftmost bit of the sequence is applied first. What is the content of the register after the 6th shift? a. 0110 b. 1011 c. 1101 d. 1110 e. 1001 f. 1010
B
19. The 74LS83 is an example of a 4-bit parallel adder. To expand this device to an 8-bit adder, you must a. Use eight adders with no interconnections b. Use two adders with the carry output of one connected to the carry input of the other c. Use two adders and connect the sum outputs of one bit to the bit inputs of the other d. Use four adders with no interconnections
B
31. Intel introduced cache memory for this microprocessor when it was launched. The Western Design Center, Inc (WDC) introduced this microprocessor in 1982 and was used as the CPU in the Apple IIe and IIc personal computers. a. IMP-16 b. CMOS 8502 c. MC 6809 d. TMS 9980
B
35. The minimal hypothetical microprocessor only includes a. ALU and set of main registers b. ALU and control logic section c. Main registers and control logic section d. ALU and segment registers
B
43. The 4-bit magnitude comparator combinational circuit generates the final output for A < B at what logic gate? a. 4 input AND logic gate b. 4 input OR logic gate c. 4 input XOR logic gate d. 4 input NOR logic gate
B
44. A race condition happens in an R-S latch when the inputs are ____ a. R = 0, S = 0 b. R = 1, S = 1 c. R = 0, S = 1 d. R = 1, S = 0
B
45. The Boolean expression.(X')' is an example of which Law/Theorem? a. Consensus theorem b. Involution law c. Idempotent law d. Commutative law
B
47. The content of a 4-bit register is initially 0110. The register is shifted 8 times to the right, with the sequence 1011 0111 as the serial input. The leftmost bit of the sequence is applied first. What is the content of the register after the 6th shift? a. 1010 b. 1011 c. 0110 d. 1101
B
49. Determine the essential prime implicants of the function F(w, x, y, z) = ∑(0, 2, 4, 5, 6, 7, 8, 10, 13, 15) a. w'x and w'z' b. xz and x'z' c. xyz' and wy d. x'yz and w'y'
B
50. A 3 x 8 decoder contains output from D0 to D7. Which output is activated high if the input expression x'yz'? a. D1 b. D2 c. D4 d. D5
B
7. The equivalent of 0.1010 base 2 in decimal is _________. a. 0.8756 b. 0.6275 c. 0.5672 d. 0.5786 e. 0.6758
B
Determine the equivalent statement of ¬Ǝx P(x). ¬∀x P(x) ∀x ¬P(x) ¬Ǝx ¬P(x) Ǝx ¬P(x)
B
How many pass will it take in order to sort the single digit array 3 5 4 1 2 using selection sort? a.) 5 b.) 4 c.) 6 d.) 10
B
Simplify F(v, w, x, y, z) = Σm (0, 1, 2, 4, 5, 8, 9, 10, 12, 16, 17, 18, 20, 21, 24, 26, 29) using Karnaugh map. v'w'y' + v'x'z' + vxz + v'y'z' + v'x'y' + vxy'z w'y' + x'z' + v'y'z' + v'x'y' + vxy'z none of the choices vw'y'+ v'x'z' + vxz + v'y'z' + v'x'y' + v'xy'z
B
Which of the ff relation from Set A {integer numbers} is considered as equivalence relation? a. R = {(a,b) | a > b or a = b } b. R = {(a,b) | a b (mod m) with m > 1} c. R = {(a,b) | a + b = 3} d. R = {(a,b) | a < b}
B
22. This flag is set when the result of an unsigned operation is too large to fit into the destination a. Zero Flag b. Parity Flag c. Overflow Flag d. Sign Flag e. Auxiliary Flag f. Carry Flag
C
25. It is an addressing mode in the Z80 that uses absolute jump, one-byte opcode and a 2 byte address a. Immediate Addressing b. Relative Addressing c. Extended Addressing d. Register Direct Addressing e. Implied Addressing f. Register Indirect Addressing
C
26. What is the result of NEG AX if AX contains FFECh? a. 0020H b. F7D8H c. 0014H d. None of the choices e. 2345H f. 3579H
C
38. A 3 input XOR can be implemented using how many 2 x 1 multiplexers? a. 4 b. 8 c. 2 d. 3
C
39. Express the following function as a sum of minterms: (xy + z)(y + xz) a. x'y'z + xy'z + xyz b. x'yz + x'y'z + xyz'+ xyz c. x'yz + xy'z + xyz' + xyz d. x'y'z + xyz' + x'y'z'
C
41. The Boolean expression.(X+Y+Z)' = X'Y'Z' is an example of which Law/Theorem? a. idempotent law b. consensus theorem c. de morgan's law d. commutative law
C
51. This is the time needed by a gate in processing its input signals before the output signal can be generated a. Threshold time b. Setup time c. Propagation delay time d. Hold time
C
23. A processor running in this mode can exploit only the lowest 20 bits of its address bus and is therefore limited to the meager 1MB memory space. a. Virtual mode b. None of the choices c. Protected mode d. Real mode
D
4. Perform the binary division 111110011 ÷ 1001 to obtain the quotient. a. 10010 b. 10101 c. 10111 d. 11011 e. None of the choices f. 11101⁸
D
48. Design a BCD to Excess-3 Code Converter. Designate the four input binary variables by the symbols A, B, C, D, and the four output variables w, x, y, and z. What is the Boolean expression of the output z with respect to inputs A, B, C and D? a. A + B'C b. C'D' + CD c. A + B(C+D) d. D'
D
6. Determine the total memory access time for a series of instructions in a system with RAM access time of 105 ns and cache access time of 10ns. Assume hit ratio of 0.75. a. 42.5ns b. 37.5ns c. 38.75ns d. 36.25ns e. 35.75ns f. None of the choices
D
6. V = {a,b,c,d,e}, E = {(a,b),(a,c),(b,c),(c,d),(c,e),(d,e)} is classified as? A Hamiltonian but not Eulerian; B neither H or E; C H and E; D E but not H
D
Determine the property or properties of the relation of the set of integers to the set of integers where (x,y) ∈ R if x is a multiple of y. a. Symmetric b. Reflexive, antisymmetric, transitive c. Reflexive, antisymmetric, symmetric, transitive d. Antisymmetric, transitive e. Reflexive, symmetric, transitive f. Reflexive, symmetric g. Reflexive, transitive
D
In the game of tic-tac-toe, every game ends with one player winning or with a draw. In a tic-tac-toe tournament, the player merely counts the number of times they win or draw. The winner is the player with the larger count. If a match between player A and player B consists of 25 games, player A scored 19 and player B scored 23, how many draws were there? a. 10 b. 21 c. 29 d. 17
D
21. The binary equivalent of decimal 1234 is _____? a. 0001 0000 1110 0001 b. 0001 0011 0010 0100 c. 0001 0010 0011 0100 d. 0010 0100 0110 1000 e. 0000 0100 1101 0010
E
Simulate the given instructions (below) and determine which among the choices is correct. Initially CF=0; AF=0; ZF=0; SF=0; PF=0. MOV AL, D6 MOV BL, E5 ADD AL, BL a. CF=1; AF=1; ZF=0; SF=1; PF=0 b. CF=1; AF=1; ZF=0; SF=0; PF=1 c. CF=1; AF=0; ZF=0; SF=0; PF=1 d. CF=1; AF=1; ZF=1; SF=1; PF=1 e. None of the choices f. CF=1; AF=0; ZF=0; SF=1; PF=1
F
40. Which of the following inputs provide a don't care in the output z given by the function F(w, x, y, z) in a BCD to excess-of-3 code converter? a. 0110 b. 1010 c. 0100 d. 0010
B
An algorithm that uses Eulerian Path/Bubble Sort to solve uses a Big-O notation of
Linear Complexity
Which of the ff vertex is called a pendant?
Leaf
Flag register contains 10000011 on its lower byte which flag registers are set as a result of executing LAHF instruction?
SF and CF
Prevent changing the location POPA which register is not loaded with data
SP or ESP
Given the following points below, what is the longest/shortest route? Gr to SW 113 mi Gr to Kal 56 mi Gr to Det 147 mi Gr to Tol 167 mi Kal to SW 137 mi Kal to Det 135 mi Kal to Tol 133 mi Tol to Det 58 mi Tol to SW 142 mi Det to SW 98 mi a.) Det- Tol- Kal- GR-Sw - Det b.) Det - Tol-Gr-Kal-Sw-Det c.) Det-GR-Sw-Tol-Kal-Det d.)Det-Sw-Tol-GR-Kal-Det
Shortest A Longest C
