Comp Org Final MC

(HW1) How many megabytes are in 10 gigabyte?

10,000 or 10 * 2^10

(HW1) How many bytes are in 10 megabytes?

10,000,000 or 10 * 2^20

(HW1) How many nanoseconds are in 13 microseconds?

13000

(HW1) How many milliseconds (ms) are in 2 seconds?

2,000

(HW1) How many kilobytes are in 2 gigabyte?

2,000,000 or 2^21

(HW1) How many microseconds are in 2 milliseconds?

2000

(Ex8) Suppose that a system uses 32-bit memory words and its memory is built from 16 1M × 8 RAM chips. How many address bits are required to uniquely identify each memory word?

22

(Ex8) Suppose that a system uses 16-bit memory words and its memory is built from 32 1M × 8 RAM chips. How many address bits are required to uniquely identify each memory word?

24

(Ex8) Suppose a system has a byte-addressable memory size of 256MB. How many bits are required for each address?

28

(HW1) How many nanoseconds are in 3 milliseconds?

3,000,000

(Ex8) Suppose a system has a byte-addressable memory size of 4GB. How many bits are required for each address?

32

(Ex8) Suppose that a 32MB system memory is built from 32 1MB RAM chips. How many address lines are needed to select one of the memory chips?

5

(HW1) How many microseconds are in 5 seconds?

5,000,000

(HW1) How many kilobytes are in 5 gigabytes?

5,000,000 or 5 * 2^20

(Ex8) Suppose we have a 1024-word memory that is 16-way low-order interleaved. What is the size of the memory address offset field?

6

(HW1) How many kilobytes are in 6 megabyte?

6,000 or 6 * 2^10

(Ex8) Suppose that a system uses 32-bit memory words and its memory is built from 16 1M × 16 RAM chips. How large, in words, is the memory on this system? How many address bits are required to uniquely identify each memory word?

8M, 23

(Exam3) Examples of hazards in pipelines include A) resource conflicts, data dependencies, and conditional branch statements B) superscalar and VLIW C) addressing modes and memory D) ILP and VLIW

A) resource conflicts, data dependencies, and conditional branch statements

(Exam3) Cache memory is typically positioned between: A) the CPU and main memory B) the CPU and the hard drive C) ROM and RAM D) none of the above

A) the CPU and main memory

(Exam3) Cache mapping is necessary because: A) the address generated by the CPU must be converted to a cache location B) cache is so small that its use requires a map C) cache is larger than main memory and mapping allows us to store multiple copies of each piece of data from main memory D) none of the above

A) the address generated by the CPU must be converted to a cache location

(Exam3) The purpose of a TLB is: A) to cache page table entries B) to cache frequently used data from memory C) to hold the starting address of the page table D) to hold the length of the page table

A) to cache page table entries

(Exam3) Fixed-length instructions: A) waste space but are fast and perform better than variable length instructions B) are more complex to decode than variable-length instructions but save space C) save space and are faster and perform better than variable-length instructions D) are less complex to decode than variable-length instructions and save space (Exam3)

A) waste space but are fast and perform better than variable length instructions

(Exam 2) A computer bus consists of data lines, ____, control lines, and power lines. A. address lines B. protocol lines C. Cycle lines D. master/slave lines

A. address lines

(Exam 2) The register that holds the address of the data to be transferred is called ____. A. memory address register B. index register C. memory buffer register D. none of these

A. memory address register

(Exam3) If a cache access requires one clock cycle and dealing with cache misses requires an additional five clock cycles, which of the following cache hit rates results in an effective access time of 2 clock cycles? A) 70% B) 80% C) 85% D) 90% E) 95%

B) 80%

(Exam3) Which of the following types of memory needs to be refreshed periodically to maintain its data? A) SRAM B) DRAM C) ROM D) all of the above

B) DRAM

(Exam3) The basic difference between RAM and ROM memory is: A) RAM is nonvolatile while ROM is volatile B) RAM is read/write while ROM Is read only C) ROM is used to store programs and data, while RAM is not D) ROM is typically specified when you buy a computer; RAM is not

B) RAM is read/write while ROM Is read only

(Exam3) The approach of using a combination of memory types to provide the best performance at the best cost is called: A) caching B) hierarchical memory C) solid state memory D) off-line memory

B) hierarchical memory

(Exam3) The tag field of a main memory address is used to determine: A) if the cache entry is valid B) if the cache entry is the desired block C) if the memory address is valid D) none of the above

B) if the cache entry is the desired block

(Exam3) To carry out a binary arithmetic operation, an accumulator architectures uses operand(s). A) zero B) one C) two D) either one or two

B) one

(Exam3) There are three basic ISA architectures for internal storage in the CPU: A) cache, RAM, and ROM B) stack, accumulator, and general-purpose registers C) cache, RAM, and registers D) load-store, cache, and RAM

B) stack, accumulator, and general-purpose registers

(Exam3) Cache replacement policies are necessary: A) to determine which cache mapping policy to use B) to determine which block in cache should be the victim block C) to decide where to put blocks when cache is empty D) all of the above

B) to determine which block in cache should be the victim block

(Exam3) A stack-organized computer uses addressing. A) indirect B) zero C) indexed D) direct

B) zero

(Exam 1)Clock speeds in today's microprocessors are measured in: A. Kilohertz B. Gigahertz C. Megahertz D. Terahertz

B. Gigahertz

(Exam 1)In 1965, one of the founders of Intel predicted "The density of transistors will double every year." This is know as: ____ A. Rock's Law B. Moore's Law C. Amdahl's Law D. Cray's Law

B. Moore's Law

(Exam 1)The Von Neumann bottleneck: A. creates collisions on an I/O bus B. describes the single processor-memory path C. is eliminated when multiple processors/cores are used D. was first invented by John Atanansoff

B. describes the single processor-memory path

(Exam 2) The ____ is a group of bits that tells the computer to perform a specific operation. A. program counter B. opcode C. register D. microoperation

B. opcode

(Exam 1) The complement (F') of F(x,y,z) = (x'+yz)(xy'+z) is: A. (x' + y' +z')(x'y+z') B. x(y' + z') + z'(x'+y) C. (x+y'z') + (x'y + z') D. (xy'z')(x'yz')

B. x(y' + z') + z'(x'+y)

(Exam3) If the opcodes field for an instruction has n bits, that means there are potential distinct operations. A) 2n B) n/2 C) 2^n D) n^2

C) 2^n

(Exam3) Cache memory improves performance by improving memory __________ while virtual memory improves performance by increasing memory _____________. A) execution time/access time B) locality/access time C) access time/address space D) organization/paging

C) access time/address space

(Exam3) Instruction sets are differentiated by which feature? A) operand storage B) operand location D) number of operands E) operations C) all of the above

C) all of the above

(Exam3) The term endian refers to a computer architecture's: A) ability to complete arithmetic operations B) ability to find the end of variable length instructions C) byte order D) address modes E) none of the above

C) byte order

(Exam3) "Locality of reference" refers to : A) data always being in cache B) programs always referencing data in RAM C) clustering of memory references D) the requirement that forces us to use a large amount of expensive memory

C) clustering of memory references

(Exam 1) There are ____ kilobytes in a terabyte A. 2^10 B. 2^20 C. 2^30 D. 2^40

C. 2^30

(Exam 1) Computer ____ concerns itself with instruction sets and formats, operation codes, data types, the number and types of registers, addressing modes, main memory access, methods, and various I/O mechanisms. A. Layers B. Organization C. Architecture D. Programming

C. Architecture

(Exam 1) We study computer ____ to become familiar with how circuits and signals collaborate to create working computer systems. A. Architecture B. Layers C. Organization D. Programming

C. Organization

(Exam 2) The ____ of a machine specifies the instructions that the computer can perform and the format for each instruction. A. control unit B. CPU C. instruction set architecture D. fetch-decode-execute

C. instruction set architecture

(Exam 2) The register that holds the actual data to be read from or written to a given memory address is called ____. A. memory address register B. index register C. memory buffer register D. none of these

C. memory buffer register

(Ex8) The _______ is responsible for fetching program instructions, decoding each one, and performing the indicated sequence of operations.

Control Unit

(Ex8) The _______ is a digital logic component that is often used in computer registers.

D Flip-Flop

(Exam 2) The _______ is a digital logic component that is often used in computer registers.

D Flip-Flop

(Exam3) Which of the following types of memory has the shortest (fastest) access time? A) cache memory B) main memory C) secondary memory D) registers

D) registers

(Exam 1) One or more NAND gates can be used to replace a(n): A. AND gate B. inverter C. OR gate D. NOR gate

D. NOR gate

(Exam 1)The level of the computer hierarchy that is composed of gates and wires is the ____. A. control level B. system software level C. machine level D. digital logic level

D. digital logic level

(Exam 2) The ____ connects the CPU to memory. A. backplane bus B. I/O bus C. expansion bus D. system bus

D. system bus

(Exam 2) An Assembler "assembles" assembly language into register transfer language (RTL) (T/F)

False

(Exam 2) Interrupt checking is typically carried out at various times during the execution of an instruction. (T/F)

False

(Exam 2)A program counter points to the memory address of the instruction that the CPU is currently executing. (T/F)

False

(Exam 2)The MAR, MBR, PC, and IR registers in MARIE can be used to hold arbitrary values. (T/F)

False

(Ex9) The __________ register that holds the address of the data to be transferred is called:

Memory Address Register

(Ex9) The __________register that holds the actual data to be read from or written to a given memory address is called.

Memory Buffer Register

(Ex9) The ______________ register keeps track of the next instruction to be fetched.

Program Counter

(Ex8) CPU time = ____ seconds.

Seconds /Program= [ Instructions / Program × Avg. Cycles / Instruction × Seconds / Cycle]

(Ex8) The _______ connects the CPU to memory

System Bus

(HW5) How is the ALU related to the CPU? What are its main functions?

The ALU is part of the CPU. The ALU carries out logical and arithmetic operations as directions by the control unit.

(HW1) In the von Neumann model, explain the purpose of the processing unit

The processing unit performs all of the arithmetic and logic functions.

(HW1) n the von Neumann model, explain the purpose of the program counter

The program counter is responsible for keeping track of the next instruction to fetch

(HW5) What are the main functions of the CPU?

To fetch, decode, and execute program instructions

(Exam 2) In high-order memory interleaving, the high-order bits of the memory address are used to select the memory bank. (T/F)

True

(Exam 2) Registers are storage locations with in the CPU itself. (T/F)

True

(Exam 2)A branch instruction changes the flow of information by changing the PC. (T/F)

True

(Exam 2)The purpose of both hardwired control units and microprogrammed control units is to raise a series of signals that carry out operations inside a computer system. (T/F)

True

(Exam2) The ALU is part of the CPU. It carries out arithmetic operations (typically only integer arithmetic) and can carry out logical operations such as AND, OR, XOR, as well as shift operations. T/F

True

(Exam2) The control unit is responsible for fetching program instructions, decoding each instruction that is fetched and performing the indicated sequence of operations on the correct data. (T/F)

True

(Exam 1)The data range for n bits signed number in 2s complement is [x,x]

[-(2^(n-1)), 2^(n-1)-1 ]

(Exam 1)The data range for n bits signed number in 1s complement is [x,x]

[-(2^(n-1)-1), 2^(n-1)-1 ]

(Exam 1)The data range for n bits signed number in signed magnitude is [x,x]

[-(2^(n-1)-1), 2^(n-1)-1 ]

(Exam 1)The data range for n bits unsigned number is [x,x]

[0, 2^(n) -1 ]

(HW5) Assume a 2^20 byte memory a.) What are the lowest and highest addresses if memory is byte-addressable? b.) What are the lowest and highest addresses if memory is word-addressable, assuming a 16-bit word? c.) What are the lowest and highest addresses if memory is word-addressable, assuming a 32-bit word?

a.) 0 to (2^20) - 1 b.) 0 to (2^19) - 1 c.) 0 to (2^18) - 1

(HW5) How many bits are required to address a 1M X 8 main memory if a.) Main memory is byte-addressable b.) Main memory is word-addressable

a.) 20 bits b.) 20 bits

(HW5) How many bits are required to address a 4M X 16 main memory if a.) Main memory is byte-addressable b.) Main memory is word-addressable

a.) 23 bits b.) 22 bits

(Ex8) A computer bus consists of data lines, __________, control lines, and power lines

address Lines

(Ex9) The __________ is a group of bits that tells the computer to perform a specific operation.

opcode