DS2 Final

The signal to be inverted is tied to the mux select input, input0 of the mux is tied to 1, and input1 of the mux is tied to 0.

A 2-to1 Mux can be used to implement an inverter if:

2

A 4-to-1 multiplexer can be built using three 2-to-1 multiplexers. Assuming each of the latter have one gate-level propagation delay, the propagation delay of the 4-to-1 multiplexer is:

5

A 4-to-16 decoder can be built using a decoder tree. How many 2-to-4 decoders with enable are necessary?

adds additional hw resources which are not necessary during normal/nominal operation.

A BIST system:

Moore FSM

A Finite State Machine (FSM) in which the outputs change only synchronous with the clock event is called a:

Concurrent and sequential events.

A State Diagram is a graphic design tool that captures:

True

A Verilog description/model may consist of a concurrent and/or procedural block of code. Functional description can be used in both of these blocks.

An entity and one or more architectures.

A circuit described in VHDL has:

True

A combinational logic circuit is one in which one or more outputs change as soon as one or more inputs change, less a non-zero propagation delay.

can detect ALL faults in a circuit.

A complete test set is one that ...

but not another task.

A function can call another function, ...

Parameterized specification in Verilog.

A generic specification in VHDL is equivalent to:

pseudo-random sequence.

A linear feedback shift register generates a:

transfers the signal value from one of its data inputs to the one single output.

A multiplexer

from 0 up to 9 and then back to 0.

A one digit BCD up counter counts

Process.

A procedural block in VHDL is called a:

True

A process in VHDL becomes active when at least one signal in the sensitivity list changes.

One or more signals in the sensitivity list change state.

A process in VHDL or always block in Verilog with a sensitivity list is entered and executed, i.e. becomes active, when:

On the right-hand-side of assignments in a procedural block.

A sensitivity list should contain all signals:

0 or 1 or Z or - (don't care)

A std_logic signal type in VHDL can have the following values:

... it is always reading logic 1.

A stuck-at-1 circuit node or wire means that ...

True

A testbench contains NO input or output ports.

None of the above.

A testbench entity in VHDL has:

looses its content when it is powered down.

A volatile memory:

(2^n)-to-1 multiplexer.

An binary function with n inputs/variables can be implemented using a:

Information about the input and output ports.

An entity in VHDL captures:

The symbol of a component in a schematic.

An entity in VHDL is equivalent to:

One or more architectures.

An entity in VHDL is or can be associated with:

... applies at the inputs ALL possible combinations.

An exhaustive test set is one which ...

reg

An output port which is assigned a value inside a procedural block (always or initial) has to also be declared as being of type:

True

Any 4-variable function can be implemented using at most three 3-input LUTs.

True

Any assignments made inside the process are NOT visible outside the process until ALL statements have been executed/evaluated.

B is greater than A.

Assume a greater-than comparator (A>B) is built using a subtractor and outputs status bits values CNVZ. If N=1 then:

the input numbers are equal.

Assume an equality comparator is built using a subtractor and outputs status bits values CNVZ. If Z=1 then:

Is NOT in error.

Assume that 1010_1111 is sent using the even parity scheme and the receiver receives: 0_1000_1111, where the MSbit is the even parity bit value. Then the even parity bit value:

One error occurred and it is being detected.

Assume that 1010_1111 is sent using the even parity scheme and the receiver receives: 0_1000_1111, where the MSbit is the even parity bit value. Which of the following statements are true?

1

Assume that the value to be sent over some data communication channel is: 1010_1111 (the underscore is used to make it easier to read, i.e. it would NOT be sent as a character!). What is the value of the odd parity bit?

000 ... 00, 100 ... 00, 110 ... 00, 111 ... 00, 111 ... 10, 111 ... 11, 011 ... 11, 001 ... 11, 000 ... 11, 000 ... 01, 000 ... 00}.

Assume the counter below is initialized to Q0Q1 ... Qn-1 = 000 ... 00. What is its counting sequence?

{100 ... 00, 010 ... 00, 001 ... 00, ... 000 ... 10, 000 ... 01, 100 ... 00}.

Assume the counter below is initialized to Q0Q1 ... Qn-1 = 100 ... 00. What is its counting sequence?

Gj and Pj.

At the cost of additional and acceptable propagation delay, the second-level carry-look-ahead reuses computation results in the form of:

Unpacked and their binary points aligned.

Before adding or subtracting two floating-point numbers, these have to be:

5

Below are the block carry-out expressions we have derived in the lecture for an 8-bit CLA using 4 x 2-bit carry generate blocks. Assuming that the maximum number of inputs to a CMOS gate is 4, the propagation delay to generate c6 is:

A greater than comparator.

Below is the block diagram of a one-digit BCD adder. What combinational logic functional block would you use to implement the "Detect if sum > 9" block?

16 memory cells and 15 2-to1 muxes.

Below is the diagram of a 3-input LUT, as used in FPGAs. Following the same structure, a 4-input LUT uses:

Detect when the sum is > 9 and if true set the Cout=1.

Below is the schematic diagram of a one-digit BCD adder. The additional 2-bit adder and Cout gate logic is necessary to:

The difference in arrival time of the clock event (rising or falling edge) at different locations on the chip or on the PCB.

Clock skew is:

More hardware resources.

Compared to a RCA, a CLA uses:

The CLA is faster, but uses significant more hardware resources.

Comparing a n-bit CLA to a n-bit RCA:

Undetermined.

DFF control signals such as RESET or SET CANNOT be:

All possible input combinations are exercised.

During exhaustive verification or testing:

All possible primary input combinations.All possible primary input combinations.

Exhaustive verification exercises:

a 4-to-1 mux.

Expansion by two variables requires at least:

canonical form.

Expansion in terms of all variables results in the:

m times.

For a nxm SSRM, where n is the size/width of the multiplicand and m is the size of the multiplier, the add/shift steps are repeated:

Have to be aligned.

For addition and subtraction, the mantissas of floating point numbers have to be:

xi AND yi

For an arbitrary bit position i the generate function is equal to:

xi OR yi

For an arbitrary bit position i the propagate function is equal to:

Covers a smaller number range than floating-point representation.

For identically sized operands, fixed-point number representation:

Covers a larger number range than fixed-point representation.

For identically sized operands, floating-point number representation:

In both concurrent and sequential blocks of code.

Functional description can be used:

True

Generic specification in Verilog allows us to design a module once and resize it as necessary at the time of instantiation.

Both, sequential and concurrent events.

Hardware description languages describe:

5

How many 2-to-4 decoders with enable are needed to built a 4-to-16 decoder?

1

How many bits can the 1-bit even parity bit scheme detect?

2

How many gate-level propagation delays are in a generic Sum-Of-Products (SOP)?

1

How many outputs are active at any point in time in a n-to-(2^n) decoder without ENable:

1111_1011

If 1011 is a 4-bit 2's-Complemented value, then the same value in an 8-bit 2's-Complement representation is:

Is NOT executed during the current cycle.

If NO signal in the sensitivity list changes, then the process:

The function is expanded by x2 and x3.

If f = ~x1(x2+x3) + x1(x2x3), then which of the following statements is FALSE, i.e. NOT TRUE?

0101_0101.

If the even indexed bit positions are set and the odd indexed values are reset, then the initialization value of an 8-bit register is:

The carry-in value is '1'.

If the propagate function p = '1' then the carry-out value will be '1' if:

there is NO a hold time violation.

If the propagation delay through the shortest path is longer than the hold time, than

The default value.

If the value of a parameter in Verilog is not specified at the time of instantiation, then the compiler/synthesizer chooses to use:

The last assignment.

If there are multiple assignments to the same signal inside the process, then when the process is exiting the signal value is equal to the:

The last assignment.

If there are multiple assignments to the same signal, then the value of the signal when the process is exited is based on:

The default value is being used.

If we don't provide a parameter value at the time of instantiation, then:

A 4-to-1 mux.

If we expand a 5-variable function in terms of 2 variables (multi-variable expansion), then to implement it we need at least:

True

In VHDL a component needs to be declared before it is used as an instance.

Any instantiation in any architecture of the working library as long as the use of the package is invoked.

In VHDL multiple components can be declared in a package. Then the scope of the declaration covers:

'0'

In VHDL, if X is of type std_logic_vector(7 downto 0), and X <= "10100101", then the value of X(3) is:

The generic map.

In VHDL, which map specifies the instantiation values for the values of generics?

'0'

In Verilog, if X[7:0] = 8'b10100101, then the value of X[4] is:

non-blocking assignments.

In Verilog, these are: f<= x1&x2;

1

In a 3-to-8 decoder without enable, how many outputs are active at any point in time?

Very responsive.

In a Mealy Finite State Machine (FSM) one or more outputs may change as soon as one or more primary inputs change. This makes this type of FSM (check all that apply):

The carry values propagate from one stage to another, from the least to the most significant bit position stage.

In a carry lookahead adder (CLA), which of the following answers is FALSE:

Only present input values, less a non-zero combinational logic path propagation delay.

In a combinational logic circuit output values depend on:

LOW or 0

In a common cathode 7-segment display the segment LED turns ON when the logic output driving it is:

Concurrently.

In a concurrent block of code statements are listed arbitrarily because these are evaluated:

Concurrently.

In a concurrent block of code the order of statements/assignments doesn't matter because these are executed/evaluated:

During a clock event and whenever any of the inputs on which these depend change.

In a finite state machine in which the output values depend on the present state value and on one or more input values, the output values may change:

9

In a one-digit BCD adder the circuit needs to carry out a 1 whenever the sum is greater than

represents the weight it carries.

In a positional number system, the position of a digit:

Sequentially.

In a procedural block statements are evaluated:

1

In a ring counter, how many output bits are high?

All carry values are computed concurrently.

In a ripple carry adder (RCA), which of the following answers is FALSE (NOT TRUE):

True

In a sequential logic circuit the values of outputs depend on present and past primary input values.

the SUM of the PRODUCTs between each digit value and the radix (or base) raised to the power of its position.

In a weighted number system, the value of a number is equal to:

2 output branches, i.e. for when the condition evaluates to true and false, respectively.

In an ASM Chart, a binary conditional box has:

Doesn't matter.

In positional/ordered port mapping/association the order of associations matters. In named mapping/association the order of associations:

the stored exponent value minus the excess value.

In the IEEE floating point formats, the stored exponent is stored in an excess form. This means that the actual exponent value is equal to:

AND gates.

In the SSRM the 2-to-1 multiplexer is used to generate the next partial product. It could be replaced by 4x2-input ...

remaining MSbits of the multiplier and incoming LSbits of the final product.

In the SSRM the mPL_Reg captures the value of the:

the first one is executed

In the Verilog CASE statement, when there is one or more matching alternative(s):

The number of 1's, including that of the parity bit, is even.

In the even parity scheme:

The concurrent block of the code.

In the example below, the Verilog conditional operator is used in:

Qb

In the figure below, which is the output of a D-FF?

Qa

In the figure below, which is the output of a D-Latch?

input plane => AND-plane => OR-plane

In the schematic of a combinational logic circuit expressed as a Sum-of-Products (SOP), a signal path from a primary input to primary output traverses the following circuit planes in order:

VHDL.

In which language is a procedural block called a PROCESS?

shift right.

Is the code below describing a: q(3) <= w; q(2) <= q(3);

no.

Latency is the total amount of time it takes in the PSRM to compute the final product of one set of input operands. This includes CL propagation delays and register Tsu and Th. Let assume that to improve the latency, i.e. shorten it, we eliminate the inter-stage registers. Can then the pipeline still work concurrently on multiple sets of operands?

C=1, V=1

On a separate sheet of scratch paper calculate the following sum and determine if overflow occurs. These operands are 8-bit 2's-C signed integers. The values of C and V are: 1 0 1 0 1 0 1 0 + 1 0 1 1 0 1 0 1

Sequentially.

Once the process is active, the statements inside the process are executed/evaluated:

it needs additional hw resources, which are not used during normal/nominal operation.

One of the disadvantages of the JTAG port and test protocol is:

Overflow has occurred if the carry in and out of the most significant bit position are different.

Overflow can be detected by applying one of the following rules:

Positional or named association.

Port mapping in VHDL can be done using:

In conditional statements evaluations (if-else for example).

Relational operators in Verilog or VHDL are used:

Sequentially.

Statements inside a procedural block (always in Verilog or process in VHDL) are executed:

True

Statements within an always block are executed sequentially.

its maximum value.

TcQ is specified in a range of values. To calculate Tmin we use:

can be replaced with test vectors that have the same values except for the bit positions that are x's.

Test vectors that contain don't cares, i.e. x's, ...

True

The 1-bit full-adder is the fundamental functional building block of any arithmetic logic circuit.

an even number of errors.

The 1-bit parity bit schemes CANNOT detect

sequential and concurrent information.

The ASM Chart captures ...

can be used to describe a n-bit ripple carry adder.

The GENERATE statement in Verilog:

True

The IF GENERATE statement in VHDL instantiates if a condition evaluation evaluates to:

A COMPLETE copy-paste of the contents of the combinational circuit's truth table.

The K-Map is a tabular-graphic tool used to infer a minimized form of a binary function. The contents of the K-Map is:

Throughput.

The PSRM improves:

True

The Perceptron weighs input evidence.

clock asynchronous.

The RESET signal below is: Reset in sensitivity list

4 sets of input operands concurrently; each is in a different stage of completion.

The SSRM processes one set of input operands at a time. By comparison, the PSRM processes ...

the procedural block of code.

The VHDL CASE statement is similar to the Select Signal Assignment, but is used in:

True

The Verilog HDL has gate level primitives defined in the language standard and recognized by the compiler/synthesizer.

True

The Verilog HDL is case sensitive.

write access cycle.

The WR control signal has to be active during a

DFF.

The always block below describes a: (posedge clock)

Named.

The association of module ports and instance ports can be positional (or ordered) OR:

Use special characters.

The binary/logic operators in Verilog:

all z and x values as don't cares.

The casex statement treats:

Functional description.

The code below represents which description of a 1-bit full-adder (1-bit FA)?

ONLY concurrent information.

The control signal table captures:

Synchronous counter.

The counter below is:

in which data is being stored, transferred, and manipulated.

The data path is the functional block ...

the computer design methodology.

The dxp_dnn_digits is designed following:

The one and only output.

The first port in the port list of a Verilog gate level primitive is:

A stimulus-response system.

The functional correctness of a logic circuit or system is verified through simulation. This comprises the following steps: stimulate primary inputs, let their effect propagate through the circuit under verification, and then capture and analyze the responses (primary output values). In a HDL based simulation this is accomplished using a testbench, which is therefore:

No matter what the carry-in value is.

The generate function indicates that a carry-out of '1' will be generated by the stage:

After the clock event.

The hold time is the amount of time the data at the D input has to be stable:

Present State (PS).

The memory elements in a FSM (DFFs) store the:

hold time.

The minimum amount of time the D input has to be stable after the clock event is called:

the setup time.

The minimum amount of time the signal has to be stable at the input D of a DFF before the clock event is called:

the multi-operand addition of the partial products

The more costly (time and resources) operation is:

FPGAs.

The multiplexer is a key functional building block in:

equal to the present state value.

The outputs of a special function register (SFR) are:

2-input NAND.

The perceptron below implements which binary function:

one 2-to-1 multiplexer.

The premise of Shannon's Expansion Theorem is that the Sum-Of-Product (SOP) form of a binary function can be separated into two terms: one that depends on the TRUE (1) and another one that depends on the COMPLEMENTED (0) value of one of the input variables. Then, expansion by a single variable will require at least ...

D-Latch.

The process below describes the behavior of a: (d, clk)

True

The sigmoid neuron weighs input evidence.

True

The statements inside an always block are executed ONLY when ONE OR MORE signals in the sensitivity list change.

EXPLICIT function information.

The truth table of a combinational logic circuit (TT of CL) contains:

X0 à x1 à x2 à x3.

The truth table of a priority encoder is shown below. Which is the correct priority order, starting with the highest priority?

the sum of the widths (sizes) of the multiplicand and multiplier.

The width (size) of the final product is equal to the

From Cin to Cout.

The worst case propagation delay in a ripple-carry adder (RCA) is:

the DFFs have to be fault-free, i.e. allow us to setup an arbitrary PS combined with a primary inputs TV.

To be able to test the NS- and Outputs-CLs:

unpacked -> manipulated -> packed.

To be able to use floating point numbers in manipulations, these have to be:

stimulated, then its effect propagated towards an output, where it is finally observed.

To be detected, a fault has to be:

is not stored, but implied when the value of the number is being reconstructed.

To convert a number to an IEEE floating point format, the number is first normalized. The integer part of the normalized value:

XORed.

To detect an error at the receiver, the even parity bit and data bits are successively:

1.

To sensitize an AND gate one sets the off-path inputs to:

0.

To sensitize an OR gate the off-path inputs are tied to:

the values of n, MC, and START (external user control input).

To sequence events in the DP and CU, the CU uses:

0

To test if a DFF is stuck-at-1 we need to scan-in and out a bit sequence that contains at least a:

True

VHDL has no built-in gate level primitives like Verilog.

True

VHDL is a strongly typed HDL.

True

VHDL requires a component to be declared before it is used as an instance.

conditional signal assignment.

VHDL which signal assignment is this?

select signal assignment.

VHDL which signal?

True

Vectors allow us to describe concisely multi-bit signals (busses).

True

We showed in class that overflow can be computed using the Cn and C(n-1) values. Alternatively, overflow can be computed using the value of Cn, X(n-1), Y(n-1), and Sum(n-1).

4

What is a practical limit for the number of inputs to a (static) CMOS gate?

The propagation of the carry values from one stage to the next.

What is the RCAs biggest performance problem?

±Infinity

When the Exponent = 111...1 and the Fraction = 000...0 the number is interpreted as:

When E switches from low to high during the high half-period of the clock.

When will the clock gating scheme below fail? gated Clock enable

D-FF.

Which 1-bit storage element is edge triggered?

Structural

Which HDL description or model is a one-to-one match with the schematic diagram of a logic circuit?

VHDL.

Which HDL was created first for documentation purposes?

y<="11"when w(3) = '1' else ...

Which code block uses the conditional signal assignment in VHDL? Caution: The capture extends from the level of the paragraph bullet upwards!

The complexity (sophistication) of connections between neurons.

Which is more important in BNNs as well as in ANNs?

Design Entry/Capture.

Which is the first design step in the design flow?

Verilog.

Which language has built-in gate-level primitives?

VHDL

Which language is more verbose?

Verilog.

Which language was created first for modeling/simulation purposes?

10100101

Which number is represented by the following Verilog description: {4'b1010, 4'h5} ?

Floating-Point.

Which number representation needs to unpack before and pack after manipulation?

Fixed-Point.

Which number representation uses the same arithmetic units that are used for integers, without any modifications.

Structural.

Which of the following descriptions is a "one-to-one" match with a schematic drawing?

AND and OR

Which of the following gate/function combinations are not fundamental, i.e. cannot be used to perform any arbitrary data processing?

it increases throughput.

Which of the following is an advantage of a digital pipeline?

the initial value of n is equal to the size/width of the multiplicand.

Which of the following statements is FALSE, i.e. NOT TRUE. As reflected in the SSRM ASM Chart, ...

Can route one input to one output only.

Which of the following statements is FALSE, i.e. NOT TRUE? A nxn crossbar:

is used in a procedural block of code.

Which of the following statements is FALSE, i.e. NOT TRUE? The FOR GENERATE statement in VHDL

A task can call another task.

Which of the following statements is true?

A testbench is NOT being synthesized.

Which of the following statements is true?

Floating-point

Which representation covers a wider range of numbers?

Timing simulation.

Which simulation type is more accurate, i.e. models real logic circuits more accurate?

Hardware Description Languages (HDLs).

Which type of languages can describe both concurrent and sequential events?

Timing.

Which type of simulation uses accurate gate and wire propagation delay?

256 locations.

With an 8-bit bus we can address a memory space with:

1

f = w1 when s = what?