Lecture 5

Serial

1 bit transmitted at a time Single data line pair and a few control lines For many applications, throughput is higher than for parallel because of the lack of electrical interference

Memory Data Register (MDR)

After a read, it contains the contents at the address given in the MAR. Before a write, it contains whatever is to be copied to the address in the MAR

Program Counter Register (PC)

Also called Instruction Pointer (IP) Contains the address of the instruction to be fetched

More Instruction Classifications

Bit manipulation instructions Flags to test for conditions Shift and rotate To implement multiplication and division Program control Control the flow of a program; includes jumps and branches Stack instructions Multiple data instructions I/O and machine control

Memory Address Register (MAR)

Contains an address in memory which is to be read from or written to.

Classification of Instructions

Data Movement (load, store) Most common, greatest flexibility Involve memory and registers What's this size of a word ? 16? 32? 64 bits? Arithmetic Operators + - / * ^ Integers and floating point Boolean Logic Often includes at least AND, XOR, and NOT Single operand manipulation instructions Negating, decrementing, incrementing, set to 0

Fetch

Decode or find instruction, load from memory into register and signal ALU

Instruction set

Design defines functions performed by the processor Differentiates computer architecture by the Number of instructions Complexity of operations performed by individual instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, modes)

Memory Capacity and Addressing Limitations

Determined by two factors: 1. Number of bits in the MAR For LMC, number of possible addresses, M = 100 (00 to 99) For an address register of width k bits, the number of possible memory addresses is M =2K 2. Size of the address portion of the instruction 4 bits allows 16 locations 8 bits allows 256 locations 32 bits allows 4,294,967,296 or 4 GB 64 bits allows 16 billion gigabytes

Instruction

Direction given to a computer Causes electrical or optical signals to be sent through specific circuits for processing

Operation of Memory

Each memory location has a unique address Address from an instruction is copied to the MAR, which finds the location in memory CPU determines if it is a store or retrieval Transfer takes place between the MDR and memory MDR is a two way register

SRAM (static RAM)

Faster and more expensive than DRAM Volatile Small amounts are often used in cache memory for high-speed memory access

Instruction Word Size

Fixed vs. variable size Pipelining has mostly eliminated variable instruction size architectures Most current architectures use 32-bit or 64-bit words Addressing Modes Direct Mode used by the LMC Register Deferred Also immediate, indirect, indexed

Parallel

High throughput because all bits of a word are transmitted simultaneously Expensive and require a lot of space Subject to radio-generated electrical interference, which limits their speed and length Generally used for short distances such as CPU buses and on computer motherboards

Instruction Format

Machine-specific template that specifies Length of the op code Number of operands Length of operands

DRAM (Dynamic RAM)

Most common, cheap, less electrical power, less heat, smaller space Volatile: must be refreshed (recharged with power) 1000's of times each second Used for main memory

Bus Characteristics

Number of separate wires or conductors Data width in bits carried simultaneously Addressing capacity Lines on the bus are for a single type of signal or shared Throughput - data transfer rate in bits per second Distance between two endpoints Number and type of attachments supported Type of control required Defined purpose Features and capabilities

Instruction Elements

OPCODE: task Source OPERAND(s) Result OPERAND Location of data (register, memory) Explicit: included in instruction Implicit: default assumed

Bus Categorizations

Parallel vs Serial buses Direction of transmission Simplex - unidirectional Half duplex - bidirectional, one direction at a time Full duplex - bidirectional simultaneously Method of interconnection Point-to-point - single source to single destination Cables - point-to-point buses that connect to an external device Multipoint bus - also broadcast bus or multidrop bus Connect multiple points to one another

ALU (Arithmetic Logic unit)

Performs calculations and comparisons Corresponds directly to the calculator in the LMC

CU (Control Unit) controls and interprets the execution of instructions

Performs fetch/execute cycle Accesses program instructions and issues commands to the ALU Moves data to and from CPU registers and other hardware components (no change in data) Corresponds to the Little Man in the LMC model Subcomponents: Memory management unit: supervises fetching instructions and data from memory I/O Interface: sometimes combined with memory management unit as Bus Interface Unit

Execute

Performs operation that instruction requires Move/transform data

Nonvolatile Memory

ROM Read-only Memory Holds software that is not expected to change over the life of the system such as firmware used for the system BIOS Flash Memory Inexpensive nonvolatile secondary storage Useful for nonvolatile portable computer storage, digital cameras, tablets, smartphones Slower rewrite time compared to RAM

Concept of Registers

Small, permanent storage locations within the CPU used for a particular purpose Manipulated directly by the Control Unit They are wired for specific functions Size is in bits or bytes (not in MB like memory) Can hold data, an address, or an instruction How many registers does the LMC have? What are the registers in the LMC?

Status Registers

Status of CPU and currently executing program Flags (one bit Boolean variable) to track conditions like arithmetic carry and overflow, power failure, internal computer error

Instruction Register (IR)

Stores actual instruction being executed currently LMC did not have this register; the LM remembered the instruction; the brain served as IR

Register Operations

Stores values from other locations (from other registers and memory locations) Data from another location can be added or subtracted from the value previously stored in a register Shift or rotate data by one or more bits Test contents of the register for conditions such as zero, positive or negative

Registers

Use of Registers Scratchpad for currently executing program Holds data needed quickly or frequently Stores information about status of CPU and currently executing program Address of next program instruction Signals from external devices General Purpose Registers User-visible or program-visible registers Hold intermediate results or data values, e.g., loop counters Equivalent to LMC's calculator Typically several dozen in current CPUs

Primary memory

holds program instructions and data and interacts directly with the CPU during program execution Equivalent to the mailboxes in the LMC

Secondary storage

is used for long term storage and is managed as Input/Output Program code and data is moved from secondary storage to primary memory for CPU execution

Every instruction

that is executed by the CPU requires memory access Memory is actually separated both physically and functionally from the CPU