RISC-V

What keyterm can you use to make comments in RISCV

#

When you do 25 << 2, what's the result

12

how many bits does imm[11:0] use

12

whats the branch offset if you end label is 4 instructions from branch

4 x 4 bytes = 16 bytes

how many registers can be used for arguments

8, a0-a7

T/F registers are numbered from 1-32

False, 0-31

What is J-format

Jumps

What does Assembler create from source files

Object files .o

How do you increment PC if branch doesn't jump

PC = PC + 4

T/F x3 and x4 are taken by global pointer and thread pointer

True

how do you do Not in RISCV

Xori x10 11111111

syntax for assigning s1 and s2 memory in stack, it's 3 lines

addi sp, sp, -8 sw, s0, 4(sp) sw s1, 8(sp)

syntax for giving back s1 and s2 memory in stack, it's 3 lines

addi sp, sp, 8 lw, s0, 4(sp) lw s1, 8(sp)

x1 = x2 - 1, make it

addi x1, x2, -1

How many bytes are in RAM

billions

what is rd

destination register which recieves result of computation

What is job of the CPU

execute a lot of instructions

what 3 fields describe what operation to perform?

funct7, funct3, opcode

U format, what does each represent: Imm[31:12], rd, opcode 20 5 7

immediate, dest, LUI OR AUIPC

where are registers located

inside the processor

S format, what does each represent: Imm[11:5], rs2, rs1, funct3, imm[4:0], opcode

offset[11:5], src, base, width, offset[4:0], STORE

imm[11:0] can hold values from which range

-2048 to 2047

how many bytes does PC hold

4 bytes

T/F x0 starts out at 0 but can be changed

False, always 0

In order to make it easier to build fast hardware, how should the CPU be designed?

Keep instruction set small and simple

diff between LUI and AUIPC

LUI writes upper 20 bits to destination with immediate value, and clears lower 12 bits, and with an addi to set the lower 12 bits, can create any 32-bit value in a register using two instructions

where is current instruction stored

Program Counter

T/F Branches change PC by a little amount

True

T/F Layouts start most left is 31 and most right is 0

True

T/F Load instructions are also I type

True

T/F R is funct7, rs2, rs1, funct3, rd, opcode (7, 5, 5, 3, 5, 7)

True

T/F RISCV instructions are same size as 1 word so they can use the same memory

True

T/F sets PC = rs + immediate

True

T/F there is a predetermined # of registers since they're in hardware

True

t/f Jalr writes PC + 4 to rd(return address)

True

What is PC Relative Addressing

Use the immediate field as the twos complement offset to PC

how to deal with or, and, xor, srl and sll that compare to constant

add i to the end of the keyword

what kind of command does jal functionName simplify?

addi ra, zero, 1016 j sum

show what mv rd, rs is shorthand for

addi rd, rs, 0

show what li rd, 13 is shorthand for

addi rd, x0, 13

why are instructions usually backwards compatible

because C code in past should still work for C code in future

if x1 == x2, go to label exit. how to code this

beq x1, x2, exit

keyword for greater than or equal to

bge

when you shift left, what happens?

bits on far right fall off and add a 0 to the right end

in these keywords like imm and funct7 etc, what's stored in them

bits that represent either an actual number or a representation for what kind of operation is happening

what is keyword for less than

blt

keyword for less than of something unsigned

bltu

do x1 != x2, go to label exit

bne x1, x2, exit

What is B-format

branches

memory addresses are in ___

bytes(multiples of 8 bits)

Where are instructions stored

code/text

lw x14, 8(x2), what does each thing in I represent

imm = +8, rs1=2, lw, rd=14, LOAD

rs2 and funct7 combine to change for I, what are they changed for

imm[11:0]

what is the term used for constants in RISCV

immediates

is word address little or big endian

little

do the following in multiple lines: A[10] = 5 + A[3]

lw x10, 12(x15) addi x10, x10, 5 sw x10, 40(x15)

x15 stores an array. get A[3] and store it in x10

lw x10, 12(x15), 12 is offset in bytes

Where is data stored

memory

shift arithmetic fails for ____ negative numbers

odd

differnce between lb, sb and lw, sb

offset is per byte, while offset for words is per

What is Jalr instruction(format I)

offset[11:0], base, 0, dest, JALR

For load instructions, what does each rep: imm[11:0], rs1, funct3, rd, opcode

offset[11:0], base, width, dest, LOAD the 12 bit signed immediate is added to the base address in rs1 to form memory address. value loaded from memory is stored in rd

or

or

shift logical right

srl

how do you save data from register calculations

store the data

What is S-format

stores

x1 = x2 - x3, make it

sub x1, x2, x3

what's the keyword for not

there is none

T/F most data we work with is in words

true

how does the object files end up leading to 1 machine code executable file

using a linker to utilize all the object files

which registers represent s0-s1

x8-x9

which registers are the saved registers

x8-x9, x18-x27

xor

xor

what is big endian

you flip the order of the byte reps. so the most significant byte rep is now the least significant

purpose of lbu

zero extends to fill register

when you do -25 << 2, what's the result

-13

how many bits of a 32 bit instruction can be used for immediate

12

What is U-format

20-bit upper immediate instructions

Each register in RISC-V for this class is how many bits

32

How many registers are in RISC-V

32

In total how big are sum of all registers in bytes

32 * 4 = 128

how many bits is 1 word

32 bits

T/F each register field holds a 5 bit unsigned integer representing the register value of that register

True

T/F entire programs can be stored in memory to be read or written just like data

True

T/F every instruction has a unique address and it's stored in memory

True

T/F if you change x11, it will change a1

True

T/F to enable extensions of RISCV to support instructions that are multiples of 16 bits in length, RISCV scales the branch offset by 2 bytes even when there are no 16 bit instructions

True

B format, what does each represent: Imm[12], imm[10:5], rs2, rs1, funct3, imm[4:1], imm[11], opcode 1 6 5 5 3 4 1 7

offset[11:5], src, base, width, offset[4:0], STORE

x1 = x2 + 1, make it

addi x1, x2, 1

What is add x1, x2, x3 doing

adds x2 to x3 and stores in x1

when you have a line adding stuff, what is this line of code called?

an instruction

and

and

how do you isolate least significant byte

andi with 0000 000FF

how do you isolate most significant byte

andi with FF00 0000

what keyword can you put before a label to ensure you go to it

j

What is I Format

register-immediate arithmetic operations and load

What is R Format

register-register arithmetic operation

what is ra

return address register to return to point of origin

What is an instruction set architecture

set of instructions a CPU implements

shift logical left

sll

what is the stack pointer label in RISCV

sp

How do you increment PC if branch does jump

PC = PC + 4*Immediate immediate is # of instructions to jump either forwards or backwards

ALU, Registers, and PC are inside Datapath, which is inside Processor(Processor also has control path), what is the purpose of PC

Program Counter is the internal register holding the byte address of next instruction to be executed

what is layout of memory RV32

Sack grows down, then text segment, then static data segment, then heap for data structures that grow and shrink, and it grows up. order is stack, dynamic data, static data, text, reserved

which register has ra

x1

which five registers are for temporary vars

x10-x11, x28-x31

which x registers are used for a0-a7

x10-x17

which registers represent s2-s11

x18-x27

which register corresponds to sp

x2

which register is the alternate link register or just a temporary var

x5

s0/fp, which register is a saved register and frame pointer

x8

for B, immediate represents which range of values

-4096 to 4094

how many bits can be stored on an instruction and why

32, think of every instruction being put temporarily in a separate register

J format, what does each represent: Imm[20], imm[10:1], imm[11], imm[19:12], rd, opcode 1 10 1 8 5 7

4 offsets, dest, JAL PC = PC + offset

T/F if you change x10, it will change a1

false, it will change a0

how do you use data in register for calculation

have to load the data

single instruction to jump and save return address

jal

diff between jal and jr

jal is called to invoke a function, jr is used to return to the function. so jal ra sum will assign the value of ra to the next line of code, then in sum, you would call jr ra which will jump back to that location in the first function. also, since you called sum, ra should be stored in memory in the first function, and if sum called another function mult, ra should also be stored in sum. You gotta keep track of what ra is pointing to at any point.

what does j actually equal

jal x0

what is a register

limited # of special locations built directly into hardware. Operations can be performed on these.

What is little endian

normal byte representation

what is rs1

specifies register containing first operand

what is rs2

specifies second register operand