CEG final

To read a character from the keyboard and load it into a register on the LC3 you must...

Check the ready bit of the KBSR then load the character data from the KBDR into a register

The instruction cycle

Constantly repeats in the same order fetching new instructions, decoding, and executing them

The MDR (Memory Data Register) is used to

Contain the requested data or the data to be sent to memory

Caches exploit temporal locality which is based on the assumption that

Data that is accessed recently is likely to be accessed again

Caches exploit spatial locality which is based on the assumption that

Data that is near the data the CPU wants to access is likely to be accessed soon

The BRx instruction on the LC3 has access to the NZP condition codes from the previous instruction because they are

Directly connected to the Finite State Machine

It is impossible to perform bitwise operations in C

False

On machines other than the LC3 interrupts are only used for I/O.

False

The primary benefit of a CPU cache is

Faster read/write speeds when compared to RAM

The program counter is incremented in the ___________ step of the instruction cycle

Fetch

The control unit

Fetches and decodes instructions and controls muxes and other internal devices

One of the key components of a register is

Flip flops

The mantissa portion of floating point numbers represent the

Fractional component of the scientific notation

An IRQ is triggered by the

I/O

The benefit of using Interrupt based I/O is...

I/O devices will demand attention when they are ready to send information

In a Branch instruction the NZP bits are used

In the control unit, to determine if we should change the PC

Which of these are not stored in the runtime stack

Instructions

The base case of a recursive function

Is the last function call in a sequence of recursive function calls

The LRU replacement algorithm may be useful because

It replaces the least recently used data in the cache

The only input we have direct access to is...

Keyboard

L1 - L3 CPU caches ranked from fastest to slowest access speeds

L1 L2 L3

L1 - L3 CPU caches ranked from largest to smallest memory capacity

L3 L2 L1

The symbolic name for an address in assembly is a

Label

The LEA instruction on the LC3 allows for

Loading an address into a register

The ALU is a combination of gates and digital circuits that allows for:

Mathematical calculations such as add, subtract, multiply, divide, and boolean operations

Latches and flip flops are an extremely simple form of

Memory

Byte addressable memory is

Memory that contains 1 byte of data per memory address

The only direct output we have access to on the LC3 is...

Monitor

The BRx instruction on the LC3 allows for

Moving the PC to a different memory address based on the result of the last instruction

Pseudo Ops are

NOT converted into machine language instructions

One of the components that is NOT in The Von Neumann Model is

Networking Unit

In the LEA instruction on the LC3, the last 9 bits of the IR are added to...

PC

The Frame Pointer always

Points to the first local variable in the frame

The Stack Pointer always

Points to the top of the stack

The MAR (Memory Address Register) is used to

Provide the address to memory that we want to either read from/write to

The instruction that allows you to exit an ISR and pop the PSR and PC from the stack is

RTI

The Processing Unit in Von Neumann Architecture contains:

Registers and ALU

One of the precursors to modern transistors was

Relays

A cache's replacement algorithm will

Replace blocks of memory stored in the cache to make way for new memory

For the instruction:AND R1, R2, #3At least two of the control signals asserted by the control unit are:

SR1 = 010 SR2MUX = 0

The SR2MUX in the LC3

Selects either a 5-bit sign extended number or a register to input into the ALU

A recursive function/subroutine

Solves tasks by calling itself

When data is accessed from memory by a CPU that has a cache it is

Stored in the cache

For a cache that is implemented using Fully-Associative Cache Mapping, data stored in memory that is accessed by the CPU is

Stored in the cache along with data that is nearby with respect to memory addresses

The ST instruction on the LC3 allows for

Taking a value from a register and putting it in a memory address within +256 or -255 addresses of the instruction

A write-through cache may be useful because

The memory in the cache and RAM are always consistent

The word size of a processor is

The size of data commonly used by registers/instructions/addresses in a particular CPU

The concept of Memory Mapped I/O is...

There are specific addresses in memory that are used to access I/O devices

All of computing is made up of a few very basic operations like AND, OR, and NOT

True

C code can be mostly compiled in LC3 assembly

True

If the program is running at a higher priority level than the interrupt request, the ISR is not called.

True

The Base + Offset memory addressing format

Uses a value inside a register plus an offset to access data in memory

The downfall of I/O Polling is...

Your program is busy waiting for I/O to be ready

The IACK

acknowledges the interrupt service request

How is data represented in a digital computer in its simplest form?

binary

Which data type does not exist natively in C?

bool

This component of a compiler highly dependent on the target machine

code generation

Pointers in C are used for

containing a reference to a variables location in memory

In the LC3 ISA there is no multiply instruction, this means to multiply two numbers we have to

create a loop using conditional branch instructions

Pass 1 of Two-Pass Assembly involves

creating a symbol table, assigning addresses to every label in the assembly code

By following the control signals we can see the LDI instruction only accesses memory once on the LC3.

false

Adding x + 33.56 in C will result in a data type of

float

When an ISR is called, the runtime stack

has the PSR and PC pushed

When an interrupt is triggered, the program jumps to a block of code called

interrupt service routine

Interrupt service routine starting addresses are stored in the

interrupt vector table

Interrupts eliminate the need for

polling

When you compile C code, the #include files are copied into source code specifically by the

preprocessor

To enable the keyboard interrupt on the LC3 you must

set bit 14 on the KBSR

This component of a compiler highly dependent on the language

source code analysis

A transistor allows us to create logic circuits because it acts as a

switch

The executable image file is

the finalized list of ML instructions that allows your program to run

The instruction set architecture is

the interface between programs and hardware

Floats are better than integers if you need

very large values or very small values with decimal precision

Assuming a Fully-Associative Cache Mapping cache with tags that are 12 bits in size: If the memory address x5FFF contains x1234, and is accessed by the CPU, the tag number in the cache corresponding to this data would be:

x5FF

Assuming a Fully-Associative Cache Mapping cache with tags that are 12 bits in size: If data with the address xF00A is brought into the cache, which memory address' data will not be brought into the cache?

xF01A

Using printf in C, if you want to print an integer you must use the syntax

%d

According to DeMorgan's Law:(a + b)' = a'b' and

(ab)' = a' + b'

Implementing the "factorial" example from class in assembly, using an input factorial(10) would result in the factorial stack frame being pushed onto the runtime stack a maximum of

10 times

The hex value: xF3 in binary is:

1111 0011

The binary value: 0111 0011 in decimal is:

115

The Von Neumann Model is

A conceptual model for designing computer architecture

A flip flop differs from a latch because

A flip flop only changes the output when there is a rising clock edge

A Half Adder differs from a Full Adder by:

A half adder does not have a carry input

What happens when the cache gets full and the CPU wants to add more to it?

A replacement algorithm replaces a block of the cache with the new one

In the JMP instruction on the LC3, R5 must pass through the...

ADDR1MUX

Combining multiple adders together allows us to

Add binary numbers that are larger than 1 bit

To write a recursive function in assembly you must write (excluding recursion via BRANCH instructions)

At least 1 subroutine

When are inputs to a function stored on the runtime stack

Before the subroutine call