Chapter 6 - Interrupts, PSW, Registers, Clocks

MIPS CP0 contains a Cause register, which contains: A. Exception code + interrupts pending B. Interrupt enables C. Exception code only D. Endianness control

A. Exception code + interrupts pending

Low priority devices should use what class of Interrupt: A. Vectored B. Maskable C. Non-Vectored D. NMI

A. Vectored

Which clocking scheme helps keep a digital system tightly synchronized (even used in the i8080): A. Rising-edge clocking B. 2-phase clocking C. Single-phase clocking D. Falling-edge clocking

B. 2-phase clocking

MIPS PSW contains: A. Flags B. All of these C. Interrupt enables D. Status register

B. All of these

Which sequential logic element is clock-edge triggered: A. NAND gates B. Flip-flops C. Latches D. ALU

B. Flip-flops

Interrupts are processed if what conditions are met: A. Pending and maskable B. Mask and global enable bits are set, it is pending and highest priority C. Enabled and pre-emptive D. Vectored with vector present on data bus

B. Mask and global enable bits are set, it is pending and highest priority

A stable system clock will help keep any digital system: A. Clocked B. Synchronized C. Asynchronous D. Indifferent

B. Synchronized

What is an Interrupt Vector: A. A byte used by an ISR to decode the identity of an interrupting device B. A byte provided by an interrupting device to identify itself C. All of these D. A byte that can be used by an ISR as a branch target offset

C. All of these

Interrupts have all these properties, except: A. A sub-class of Exception B. Preemption C. Cause no pipeline flush D. Priority

C. Cause no pipeline flush

Registers are composed of a linear array of what logic element: A. RS latches B. NAND gates C. D flip-flops D. ALU

C. D flip-flops

MIPS CP0 contains which registers: A. BadVAddr + Config B. EPC + Count C. all of these D. Cause + Status

C. all of these

What is used to distribute a system clock to all of the system: A. Quartz crystal B. Control bus C. Registers D. PLL tree

D. PLL tree

What type of analog circuit is necessary for providing a stable clock: A. D flip-flops B. ALU C. Inductors D. PLL, including a VCXO

D. PLL, including a VCXO

PSW contains: A. Process Software B. Program Software C. Priority Sequence Word D. Program Status Word

D. Program Status Word

What type of logic block is necessary for an FSM - Finite State Machine: A. Decoders B. ALU C. Latches D. Registers

D. Registers