CS 310 TEST 4

Set P5, P4, P3

(Destination) Controls writing to memory or a register

MIPS Input & Output

- No input/output instructions

How does MIPS I/O Work?

- is a memory mapped to get input used a load from memory location associated to memory device. - to get output, use a STORE to a memory location associated with an output device.

8086 Registers

-EAX, EBX, ECX, EDX ( 32 bits) -AX, BX, CX, DX (rightmost low-order 16 bits from above). -AH, AL, BH, BL, CH, CL, DH, and DL (leftmost and right most 8 bits from above). EX: EAX = 32bits | | AH=8 bits | AL=8 bits | AX=16 bits -ESI - source index and EDI - destination index used to implement array indexes. -ESP - Stack pointer -EBP - Base pointer -CS, DS, ES, FS, GS, SS - 16 bit segment regiters -EIP - Instruction Pointer -EFLAGS - holds carry out in arithmetic

8086 Data

1. Integers - 2's complement representation. -May be declared in assembly language using hexadecimal(h), octal(q), binary(b) or decimal(default). -May be of size BYTE, WORD, DWORD, or QWORD ex: THREE, BYTE 3 11b 3h 3q 2. Character -ASCII

Intel 8086 Details:

1. Memory 2. Registers 3. Data 4. Instruction Set 5. Instruction Format 6. Addressing Modes 7. I/O

Bus Standards

1. Synchronous bus - clocked (events controlled by the clock tick or the clock rate). -May have a problem with clock skew (drift in the clock). -Requires bus be kept as short as possible, 2. Asynchronous bus - control lines coordinate the operations. -Require handshaking protocol to enforce timing. -Scales better with technology and support wider variety of devices.

- System -

connects the CPU, memory, and other internal components.

What is Computer Level Hierarchy

• Each virtual machine layer is an abstraction of the level below it. • The machines at each level execute their own particular instructions, calling upon machines at lower levels to perform tasks as required. • Computer circuits ultimately carry out the work.

Set P2, P1, P0

(Source) Control reading from memory or a register

IBM Data Types

- Integers 2's complement (16 or 32 bits) - Packed decimal integers - Zoned decimal integers ex: [F1][F2][F3] -> [1 2][3 F] - Zones of C means signed + F unsigned + B or D means - - Character uses EBCDIC (Extended Binary Coded Decimal Interchange Code is an eight-bit character) - Floating point - Single Precision is 32-bits ex: 1 7 24 [S][ exponent ][ fraction ] - Double Precision ex: 1 7 24 [S][ exponent ][ fraction ] -118.625 = 1110110.101 = .01110110101 x 2^8 =-.76A000 x 16^2

MIPS Instruction Set

- Loads & store (only instructions which access memory) - It has arithmetic & Logic for Integer - Shifts - Jump and Branch - Floating Point Arithmetic - Data Transfer - Exception Signals

Program Execution Transfer Instructions (Branch & Loop Instructions)

-Instruction to transfer the instruction during an execution without any condition (CALL, RET, JMP). - Instruction to transfer the instruction during an execution with some conditions (JA, JAE, JBE, JC, JE, JG, JGE, JL, JLE, JNC, JNE, JNO).

Arithmetic Instructions

-Instructions to perform addition (ADD, ADC, INC, AAA). -Instructions to perform subtraction (SUB, SBB, DEC, NPG, CMP, AAS). -Instructions to perform multiplication (MUL, IMUL, AAM). -Instruction to perform division (DIV, AAD).

Bit Manipulation Instructions

-Instructions to perform logical operation (NOT, AND, OR, XOR) -Instructions to perform shift operations (SHL, SHR). ex: Shift 2, Multiply Ex: 0 1 1 0 Divide Ex: 0 1 1 0 / / / / \ \ \ \ 1 1 0 0 0 0 1 1 3 x 2 = 6 6 x 3 = 2

8086 Instruction Format

-Length varies from one to six bytes -A number of operands vary from zero to two operands: 1. May be a register 2. May be a register & a memory location 3. May be a register an immediate operand 4. May be an immediate operand & a memory location

Real World Architectures

-Marie share many features with modern architectures but it is not an accurate depiction of them. -Intel architecture which is CISC machine and MIPS, which is a RISC machine. -8086 - the classic Intel architecture, it was born in 1979. It is a CISC architecture. (more than 200 instructions). -IBM adopted 8086 for its framed PC, which was released in 1981. -The 8086 operated on 16-bit data words and supported 20-bit memory addresses. -Later, to lower costs, the 8-bit 8088 was introduced. Like the 8086, it used 20-bit memory addresses. -8086 had four 16-bit general purpose registers that could be accessed by the half-word. EAX, EBX, ECX, EDX with EAX sometimes used as an accumulator for many arithmetic operations. -It also had a flags registers, an instruction register, and a stack accessed through the values in two other registers, the base pointer and the stack pointer. -The 8086 had no built-in floating-point processing. -In 1980, Intel released the 8087 numeric coprocessor but few users elected to install them because of their high cost. -In 1985, Intel introduced the 32-bit 80386. -The 80486, introduced in 1989, was an 80386 that had built-in floating point processing and cache memory. -The 80386 and 80486 offered downward compatibility with the 8086 and 8088. -Software written for the smaller-word systems was directed to use the cover 16-bits of the 32-bits registers. -Intel's Pentium 4 introduced a brand new Net Burst architecture. -Speed-enhancing features include: 1. Hyperthreading 2. Hyperpipelining 3. Wider instruction pipeline 4. Execution trace cache (holds decoded instructions for possible reuse) multilevel cache and instruction pipelining. -Intel along with many others is marrying many of the ideas of RISC architectures with microprocessors. -MIPS family of CPUs has been one of the most successful in its class. -In 1986 the first MIPS CPU was announced. It had a 32-bit word size and could address 4GB of memory. -MIPS was one of the first RISC microprocessors. -Original MIPS architecture had only 55 different instructions as compared with 8086 which had over 200. -MIPS was designed with performance in mind. It is load/store architecture, meaning that only the load and store instructions can access memory. -A large number of registers in the MIPS architecture keeps bus traffic to a minimum.

8086 Memory

-Memory size 1 MB or 2^20 -Byte addressable is 20 bits -Word is 16 bits Double Word is 32 bits Quad word is 64 bits

Processor Control Instructions

-These instructions are used to control the instruction action by setting/resetting flag values. -Used to execute the given instructions for number of times. List of instructions: 1. Loop 2. Loope/Loopz 3. LoopNE/LoopNZ 4. JCXZ

Data Transfer Instructions

-These instructions are used to transfer the data from the source operand to destination operand. -Instructions to transfer a word (ex MOV). -Instruction for input and output port transfer (IN, OUT). -Instructions to transfer the address (LEA, LDS, LES) -Instructions to transfer flag registers (ex LAHF, DSAHF)

Interrupt Instructions

-Used to call the interrupt during program execution. -INT - used to interrupt the program during execution and calling service specified. -INTO - OF = 1, interrupt during execution. -RTT = return from interrupt service to the main program.

MARIE Datapath

0 - Main Memory 1 - MAR 2 - PC 3 - MBR -> AC & ALU -> AC 4 - AC -> MBR & ALU 5 - InREG 6 - OutREG 7 - IR

Marie 7 registers are:

1. Accumulator (AC) 16 bit register that holds a conditional operator(e.g. "less than") or one operand of a two-operand instruction. 2. Memory address register, MAR, a 12-bit register that holds the memory address of an instruction or the operand of an instruction. 3. Memory buffer register, MBR a 16-bit register that holds the data after its retrieval from, or before its placement in memory. 4. Program counter, PC, a 12-bit register that holds the address of the next program instruction to be executed. 5. Instruction register, IR, which holds an instruction immediately preceding its execution. 6. Input register, InREG, an 8-bit register that holds data read from an input device. 7. Output Register, OutREG, an 8-bit register, that holds data that is ready for the output device.

4 Categories of bus arbitration

1. Daisy Chain: permissions are passed from the highest priority device to the lowest. 2. Centralized parallel: each device is directly connected to an arbitration circuit. 3. Distributed using self-detection: devices decide which gets the bus among themselves. 4. Distributed using collision detection: any device can try to use the bus. If its data collided with the data of another device, it tries again.

8086 Instruction Set

1. Data Transfer Instructions 2. Arithmetic Instructions 3. Bit Manipulation Instructions 4. String Instructions 5. Program Execution Transfer Instructions (Branch & Loop Instruction) 6. Processor Control Instructions 7. Iteration Control Instructions 8. Interrupt Instructions

Addressing Modes

1. Immediate 2. Register Mode 3. Based Displacement D(B) 4. Indexed - Base: Displacement D(X,B) ex: register 7 = 00 00 00 2A register 9 = 00 00 01 00 address = D+(X)+(B) D(X,B) = 14(7,9)

8086 Addressing Modes

1. Immediate addressing mode - the data operand is a part of the instruction itself is know as immediate addressing mode. 2. Register addressing mode - the register is the source of an operand for an instruction. 3. Direct addressing mode - the effective address of the memory location is written directly in the instruction. 4. Register indirect addressing mode 5. Based addressing mode 6. Indexed addressing mode 7. Based - index addressing mode 8. Based - indexed with displacement mode

Types of Buses by use

1. Processor-memory-Bus-Short, high speed bus matched to the memory system to maximize transfer of data. 2. Input/Output - Longer and allow for many types of devices with varying bandwidths (compatible with different architectures. 3. Back-plane - built into the chassis of the machine connecting the processor, input/output devices and the memory. 4. PC Buses - System - connects the CPU, memory, and other internal components. - Expansion - connects external devices, peripherals, expansion slots and input/output parts to rest of computer. - Local - data bus that connects a peripheral directly to the CPU.

The Bus

1. The CPU stores data with other system components by way of a data ___. - is a set of wire that simultaneously convey a single bit along each line. ex: Serial Port-----Modem ALU---------Control Unit -Point to Point is faster than multi-point. 2. Two categories are commonly found in computer system are point to point and multi-point buses. 3. Consist of data lines, control lines, and address line. 4. While the data lines convey bits from one device to another, control lines determine the direction of data flow, and when each device can access it. 5. Address lines determine the location of source or destination of the data. ex: 10-bit lone for 1024, 2^10 power. 6. Because a multi-point is a shared resource access to it is controlled through protocols, which are built into the hardware. CPU-Memory-Disk Controller- Disk | | | | ----------------------------- | Computer - Disk Controller

Instruction Processing

1. The fetch-decode-execute-cycle is the series of steps that a computer carries out when it runs a program. 2. We first have to fetch an instruction from memory and place it into the IR. 3. Once in the IR, it is decoded to determine what needs to be done next. 4. If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR. 5. With everything in place, the instruction is executed. ex: start -> copy PC to MAR -> Copy the contents of memory address MAR to IR. Increment PC by 1 -> Decode the instruction and place bits IR[11-0] in MAR -> Instruction requires operand? -if-YES-> Copy contents of memor at address MAR to MBR. -if-NO-> execute the instruction then loop.

Register:

1. hold data that can be readily accessed by the CPU. - Very expensive than ram. -General or special. 2. They can be implemented using D Flip-Flops - 32-bit register requires 32 D flip-flops 3. May be general purpose or special purpose.

IBM Register

16 general purpose registers 32 bit each numbered, 0 -15. 4 floating point registers, 64 bits each numbered 0, 2, 4, 6 PSW - Program Status Word of 64-bits

IBM Instruction Formats (2 operand machine)

2, 4, or 6 bytes long = 20 formats most commonly used: RR = Register to Register 16-bits RX = Register to Indexed Storage 32-bits RS = Register to storage 32-bits SI = Storage Immediate 32-bits SS = Storage to Storage 48-bitss

IBM memory

2^24 byte addressable halfword = 2 bytes on an address (divisible by 2) Fullword = 4 bytes on a fullword boundary (divisible by 4) doubleword = 8 byts on a doubleword boundary (divisible by 8) ex: 0 1 2 3 \ / \ / 1st fullword 2nd FW \ / 1st double word

MIPS Memory

2^32 byte addressable Big endian (denoting or relating to a system of ordering data in a computer's memory whereby the most significant) halfword = 16-bits word = 32-bits word boundary has addressable divisible by 4.

MIPS Instruction Format

3 formats all 32-bits, 6-bit opcode 3 operands

MIPS Registers

32 general purpose 32-bits registers 32 floating point 32 bits register $0-31, PC, IR

IBM Interrupts

5 Categories: 1. Input & Output 2. Program Interrupts (it happen when divided by zero, an overflow, protection exception, addressing exception) 3. Supervisor Call 4. External 5. Machine Check

IBM Instruction Set (greater than 200)

7 Categories: 1. Arithmetic: halfword, fullword, packed, floating point single, double, extended. 2. Logical Instructions (comparison) 3. Branching 4. Data Transfer: Load(L) & Store (ST) 5. Shift & Rotate 6. Control Flow: control the loop 7. Privileged

Microcode

A layer of hardware-level instructions involved in the implementation of higher level machine code instructions in many computers and other processors. Retrieved during each clock cycle.

Two's Complement

A representation of negative integers that is formed by changing each 1 bit to a 0 and each 0 bit to a 1 and then adding 1.

IBM Frame is a example of?

CISC - Complex Instruction Set Computer.

The CPU time required ti run a program is given by general performance equation:

CPU Time = seconds/program = instructions/program * avg cycle/instructions * seconds/avg cycle

CISC

Complex Instruction Set Computer. Have a large number of instructions, of variable length, with complex layouts.

Advantage and disadvantage of Sign-magnitude

Easy for human to read negative 0 and positive 0

8086 Input and Output

IN - read a byte or word from the provided port to the accumulator. OUT - used to send out a byte or word from the accumulator to the provided port.

Bus Arbitration

Is a master-slave configuration, where more than one device can be the bus master, concurrent bus master requests must be arbitrated

MIPS

Microprocessor without Interlock Pipeline Service is a load/store architecture, which means that all instructions (other than the load and store instructions) must use registers as operands (no memory operands are allowed).

RISC

Reduced Instruction Set Computer. This is to simplify instructions so they can execute more quickly. Examples are Pentium family and the MIPS architectures

MIPS Addressing Modes

Register Immediate Base Relative PC Relative Indirect

The MARIE's control signal consist of

Register controls: P0 - P5 ALU controls: A0 - A3 Timing: T0 through T7 Counter reset: Cr (synchronized, counter reset)

Representations for signed integer

Sign magnitude One's Complement Two's Compliment

MIPS Data Types

Signed Integer (2's complement) Floating Point IEEE 754 single & double precision

IEEE-754

Single provision floating point Standard 8 bit exponent 23 bit significand 1 bit sign double is 64 bits = 11 bit exponent , 54 bits significand

PC Buses

System, Expansion, and Local

MARIE's microoperation codes along with the corresponding RTL

The advantages of micro programmed control are that it can support very complicated instruction and only the microprogram needs to be change if the instruction set changes (or an error is found).

Range

The difference of a numeric integer between the longest and smallest values that can be expressed. It came from the exponent.

How does the computer access a memory location corresponds to a particular address?

We observe that 4M can be expressed as 2^2 * 2^20 = 2^22 words - Memory locations for this memory are numbered through 2^22-1. - Required at least 22 address lines - The address lines count from 0 to 2^22-1 in binary. Each line is either "on" or "off" indicating the location of the desired memory element. High order | 11 bits | 4 bits | Low order | 4 bits | 11 bits | 4 bits select the chip.

We can improve CPU throughput

When we reduce the number of instructions in a program, reduce the number of cycles per instruction or reduce the number of nanoseconds per clock cycle.

String Instructions

a group of bytes/words and their memory is always allocated in a sequential order.

Byte

a group of eight bits, smallest possible addressable unit of computer

Nibble

a group of four bits

MARIE's RTL ALU 3 operations

add, subtract and clear + fourth is "do nothing"

Hamming codes

code words formed by adding redundant check bits, or parity bits to data word. The Hamming distance between two code words is the numbers of bits in which two code words differ. Ex: 10001001 10110001 Hamming distance of 3 Minimum Hamming distance for a code is the smallest Hamming distance between all pairs of words in the code. The Minimum Hamming distance for a code D(min) determines its error detecting and error correcting capability.

- Expansion - .

connects external devices, peripherals, expansion slots and input/output parts to rest of computer

- Local -

data bus that connects a peripheral directly to the CPU.

Processor-memory-Bus-Short,

high speed bus matched to the memory system to maximize transfer of data.

The fetch-decode-execute-cycle

is the series of steps that a computer carries out when it runs a program.

Minimum Hamming distance for a code

is the smallest Hamming distance between all pairs of words in the code. ex: Code words A=0011 d(A,B)=1 d(B,D)=3 B=1011 d(A,C)=1 d(C,D)=1 C=0001 d(A,D)=2 D=0000 d(B, C)=2 it determines its error detecting and error correcting capability.

the von Neumann bottleneck.

o A single data path between the CPU and main memory. • This single path is known as

Control Store

part of a CPU's control unit that stores the CPU's microprogram

One's Complement

represent negative values by taking the complement of each bit

Micprogram

stored in firmware, which is also called the control store. A Microcode instruction is retrieved during each clock cycle.

control lines determine

the direction of data flow, and when each device can access it.

Address lines determine

the location of source or destination of the data.

Bus

the pathway along which data and instructions travel.

IBM Input & Output

uses specialized processors called I/O channels to perform I/O which is one of the earliest forms of parallelism.

Non-von Neumann Models

• Conventional stored-program computers have undergone many incremental improvements over the years. • These improvements include adding specialized buses, floating-point units, and cache memories, to name only a few. • But enormous improvements in computational power require departure from the classic von Neumann architecture. • Adding processors is one approach. Non-von Neumann Models • In the late 1960s, high-performance computer systems were equipped with dual processors to increase computational throughput. • In the 1970s supercomputer systems were introduced with 32 processors. • Supercomputers with 1,000 processors were built in the 1980s. • In 1999, IBM announced its Blue Gene system containing over 1 million processors. • Multicore architectures have multiple CPUs on a single chip. • Dual-core and quad-core chips are commonplace in desktop systems. • Multi-core systems provide the ability to multitask o E.g., browse the Web while burning a CD • Multithreaded applications spread mini-processes, threads, across one or more processors for increased throughput.

The von Neumann Model

• Inventors of the ENIAC, John Mauchley and J. Presper Eckert, conceived of a computer that could store instructions in memory. • The invention of this idea has since been ascribed to a mathematician, John von Neumann, who was a contemporary of Mauchley and Eckert. • Stored-program computers have become known as von Neumann Architecture systems • These computers employ a fetch-decode-execute cycle to run programs as follows . . . • The control unit fetches the next instruction from memory using the program counter to determine where the instruction is located. • The instruction is decoded into a language that the ALU can understand. • Any data operands required to execute the instruction are fetched from memory and placed into registers within the CPU. • The ALU executes the instruction and places results in registers or memory

The Computer Level Hierarchy

• Level 6: The User Level o Program execution and user interface level. o The level with which we are most familiar. • Level 5: High-Level Language Level o The level with which we interact when we write programs in languages such as C, Pascal, Lisp, and Java. • Level 4: Assembly Language Level o Acts upon assembly language produced from Level 5, as well as instructions programmed directly at this level. • Level 3: System Software Level o Controls executing processes on the system. o Protects system resources. o Assembly language instructions often pass through Level 3 without modification. • Level 2: Machine Level o Also known as the Instruction Set Architecture (ISA) Level. o Consists of instructions that are particular to the architecture of the machine. o Programs written in machine language need no compilers, interpreters, or assemblers. • Level 1: Control Level o A control unit decodes and executes instructions and moves data through the system. o Control units can be microprogrammed or hardwired. o A microprogram is a program written in a low-level language that is implemented by the hardware. o Hardwired control units consist of hardware that directly executes machine instructions • Level 0: Digital Logic Level o This level is where we find digital circuits (the chips). o Digital circuits consist of gates and wires. o These components implement the mathematical logic of all other levels.

IEEE

• The Institute of Electrical and Electronic Engineers (IEEE) • Promotes the interests of the worldwide electrical engineering community. • Establishes standards for computer components, data representation, and signaling protocols, among many other things.