CS281R Final Exam Study Guide -UMKC 2021

Finish translating this assembly instruction to a machine instruction: add $t6, $t5, $t4 __a___ __b__ __c__ __d__ 00000 __e___ 1) a 2) b 3) c 4) d 5) e

1) 000000 (add's opcode is 00000) 2) 01101 (The second field is the first source register, in this case $t5, whose encoding is 01101.) 3) 01100 (The third field is the second source register, in this case $t4, whose encoding is 01100.) 4) 01110 (The fourth field is the destination register, in this case $t6, whose encoding is 01110.) 5) 100000 (The add instruction uses both the first and sixth fields to specify an add: 000000 and 100000, respectively .Note that the fifth field is unused, shown above as 00000.)

Finish translating this assembly instruction to a machine instruction: addi $t3, $t4, 7 __a___ __b__ __c__ 0000000000___d___ 1) a 2) b 3) c 4) d (just the last 6 bits of the immediate field)

1) 001000 (The 6-bit opcode for addi is 001000. That opcode is unique to addi, so the hardware knows how to interpret the rest of the instruction.) 2) 01100 (The second field is the source register, in this case $t4. Note that the ordering of the registers differs from the assembly, but the hardware knows.) 3) 01011 (The third field is the destination register, in this case $t3, whose encoding is 01011.) 4) 000111 (7 in binary is 111. Extending to 16 bits is 0000000000000111. This question just asked for the last 6 bits, so 000111.)

In binary addresses below, the .. means enough 0's to form the indicated number of bits. For instruction beq $t0, $t1, Label, beq's next instruction's address is 40, and Label's address is 60. What is the offset in decimal, before any adjustments for filling the 16-bit immediate field? a) 20 b) 40 c) 60

a) 20 (The offset is the difference between the next instruction's address and the label's address, so 60 - 40 or 20.)

For a j instruction, the immediate is _____ bits. a) 26 b) 32

a) 26

Given a system with memory alignment, which value of $t5 results in successful execution of the instruction sw $t0, 0($t5)? a) 5224 b) 5234 c) 5213 d) 5214

a) 5224

Which of the following statements about cache write policy is NOT true? a) A cache entry with dirty bit = 1 means the data inside is safe to be replaced. b) A write back approach is typically faster than a write through approach. c) A write back approach is not suitable for multiple processors accessing the same memory. d) A dirty bit is used to implement a write back approach.

a) A cache entry with dirty bit = 1 means the data inside is safe to be replaced.

Which of the following statements about cache performance is true? a) A larger cache size results in higher hit rate. b) A larger cache size results in faster access. c) The higher associativity a cache has, the less expensive to implement. d) A larger block size always results in lower miss rate.

a) A larger cache size results in higher hit rate.

Given $t1 = 8, $t2 =5, $t3 = 7, and $t4 = 3, what is the instruction sequence that stores the values of 3 + 7 in both register $t5 and the memory location DM[1005]? a) Add $t5 = $t4 + $t3 Store $t5 to DM[1005] b) Add $t5 = $t2+ $t3 Store DM[1005] to $t5 c) Add $t5 = $t4 + $t3 Store DM[1005] to $t5 d) Add $t5 = $t2 + $t3 Store $t5 to DM[1005]

a) Add $t5 = $t4 + $t3 Store $t5 to DM[1005]

Indicate the category for the instruction. Load t0 with DM[5255] a) Data transfer b) ALU c) Branch

a) Data transfer

Cache is usually built using _____. a) SRAM b) DRAM

a) SRAM

A processor executes each machine instruction one at a time (conceptually). a) True b) False

a) True

The register file in MIPS has 32 registers. a) True b) False

a) True

Memory alignment

The restriction of word addresses to multiples of 4 (or other multiples for different processors).

Given the following register file contents, what is the value of $t3 after executing the instruction sequence? bne $t1, $t2, L1 addi $t3, $t3, 5 L1: addi $t3, $t3, 5 Register File $t1 -- 5 $t2 -- 5 $t3 -- 10 a) 20 b) 25 c) 10 d) 15

a) 20

Given a memory location stored in $t2, which of the following instructions loads the content of the memory to register $t0? a) lw $t0, 0($t2) b) lw $zero, 0($2) c) lw $t2, 0($t0) d) lw $t2, 0($zero)

a) lw $t0, 0($t2)

For a subroutine with 2 arguments and no return value, which instruction loads the second argument to $t5? a) lw $t5 0($sp) b) lw $t5 8($sp) c) lw $t5 4($sp) d) lw $t5 -4($sp)

a) lw $t5 0($sp)

Relative to the processor, a cache typically resides _____. a) on-chip b) off-chip

a) on-chip

Complete the assembly to push the value held in $t3 to the stack. ____________________ sw $t3, 0($sp)

addi $sp, $sp, -4

In binary addresses below, the .. means enough 0's to form the indicated number of bits. For instruction beq $t0, $t1, Label, the beq instruction's address is 40, and Label's address is 60. What is the machine instructions 16-bit immediate field? a) 0..010000 b) 0..0100 c) 0..0101

b) 0..0100 (The next instruction's address is 44, so the offset is 60 - 44 or 16. In binary, 16 is 0..010000. The rightmost 00 is omitted, yielding 0..0100.)

In binary addresses below, the .. means enough 0's to form the indicated number of bits. For a branch instruction, the offset is determined to be 32 (before adjustments). What will the 16-bit immediate field be? a) 0..010 b) 0..01000 c) 0..0100000

b) 0..01000 (32 is 0..0100000 in binary. The rightmost two bits are known to be 00, so are omitted, leaving 0..01000.)

In the binary addresses below, the .. means enough 0's to form the indicated number of bits. For instruction j Label, the address of Label is determined to be 40. What is the machine instruction's immediate field? (Each choice is 26 bits) a) 0..0101000 b) 0..01010 c) 0..0101

b) 0..01010 (0..0101000 is 40 in binary. The rightmost two bits are known to be 00, so are omitted, yielding 0..01010.)

For instruction beq $t0, $t1, Label, the beq instruction's address is 20, and Label's address is 16. What is the machine instruction's 16-bit immediate field? a) 1..1111 b) 1..1110 c) 0..0001 d) 0..00010

b) 1..1110

Given the following data memory (DM) contents and assuming $t1 holds 416, what is the value of $t0 after executing the instruction sequence? lw $t0, -4($t1) Data Memory 400 -- 25 404 -- 20 408 -- 15 412 -- 10 416 -- 5 a) 5 b) 10 c) 25 d) 20

b) 10

For a sub instruction, the first 6 bits are 000000, and the last 6 bits are _____ . a) 100000 b) 100010

b) 100010

Compared to memory, a typical cache might be _______. a) 10x smaller b) 1000x smaller c) 10x larger

b) 1000x smaller

addi uses _____ bits for the immediate value. a) 5 b) 16

b) 16

Assume the program stack is used for all subroutine arguments and return values. What is the stack frame size for a subroutine with one argument and one return value? a) 1 b) 2

b) 2

Given the following register file contents, what will be the value of $t3 after executing the instruction sequence? Register File $t1 -- 2 $t2 -- 4 $t3 -- 6 a) 0 b) 2 c) 3 d) 1

b) 2

Given the following data memory (DM) contents and assuming $t0 holds 7004, what is the offset value of the lw instruction if the content at address 7008 is being accessed? lw $t1, _____($t0) Data Memory 7000 -- 25 7004 -- 20 7008 -- 15 a) 7008 b) 4 c) 1 d) 0

b) 4

Given an 8-bits memory address and a 2-way set-associative cache with 64-bytes capacity and 2-byte block size, how many bits is index and tag? Index = _____ bits, Tag = _____ bits a) 2, 4 b) 4, 3 c) 3, 4 d) 4, 2

b) 4, 3

Which of the following statements about cache is NOT true? a) A cache hit means that an item is found in the cache. b) A cache is faster and has higher capacity than memory. c) A cache typically resides on-chip with the processor. d) SRAM is faster than DRAM

b) A cache is faster and has higher capacity than memory.

Indicate the category for the instruction. Subtract t6 = t1 -t4 a) Data transfer b) ALU c) Branch

b) ALU

Complete the following instruction sequence to add the values in registers t0 and t1 and store the result in DM[5007]. Store t6 to DM[5007] a) Add t2 = t0 + t1 b) Add t6 = t0 +t6 c) Add t6 = t0 + t2

b) Add t6 = t0 +t6

Which of the following cache access sequences is correct? a) Check index bits, check tag bits, check valid bit. b) Check index bits, check valid bit, check tag bits. c) Check valid bit, check index bits, check tag bits. d) Check valid bit, check tag bits, check index bits.

b) Check index bits, check valid bit, check tag bits.

A subroutine's instructions must be duplicated each time the subroutine is called. a) True b) False

b) False

A typical register file has 1G or more registers. a) True b) False

b) False

An assembly program is placed into a processor's instruction memory. a) True b) False

b) False

An executable file is convenient for humans to read. a) True b) False

b) False

Different MIPSzy instructions have different numbers of bits. a) True b) False

b) False

In little-endian format, 10000000 would become 00000001. a) True b) False

b) False

Little-endian processors are faster than big-endian. a) True b) False

b) False

MIPS is the most popular processor in commercial products today. a) True b) False

b) False

The register file in MIPSzy has 32 registers. a) True b) False

b) False

add and sub make use of all 32 bits. a) True b) False

b) False

A subroutine may have up to 1024 instructions. a) True b) False

b) False (no limit)

Simple processor X only requires 1 MB of memory, which can fit entirely on-chip with X as SRAM. Is a cache necessary? a) Probably b) Probably not

b) Probably not

Which of the instruction sequences is equivalent to the following expression? if ($t1 != $t2) $t3 = $t3 - 1 a) bne $t1, $t2, L1 addi $t3, $t3, -1 L1 : b) beq $t1, $t2, L1 addi $t3, $t3, -1 L1: c) bne $t1, $t2, L1 sub $t3, $t3, 1 L1: d) beq $t1, $t2, L1 sub $t3, $t3, 1 L1:

b) beq $t1, $t2, L1 addi $t3, $t3, -1 L1:

In the binary addresses below, the .. means enough 0's to form the indicated number of bits. Instruction j Label is at address 0000..1000 (32 bits). Given an immediate field of 0..0111 (26 bits), what address will the CPU construct? a) 0000..0111(32 bits) b) 0000..011100(26 bits) c) 0000..0111000(32 bits)

c) 0000..0111000(32 bits) (The CPU appends 00 on the right, and prepends 0000, yielding the needed 4 + 26 + 2 = 32 bits.)

If 1000 memory accesses require 10,000 cycles, how long might 1000 accesses to cache require (assuming the items being accessed are already in the cache)? a) 100,000 cycles b) 10,000 cycles c) 1,000 cycles

c) 1,000 cycles

Assume the following initial values: t2 = 7, t3 = 1, and t4 = 9. What is in t4 after the following: Add t3 = t3 + t2 Add t4 = t4 + t3 a) 9 b) 10 c) 17

c) 17

Given the cache and its content below, what happens if a processor reads from memory address 10101? Index -- Cache data -- tag 00 10 101 01 5 111 10 15 100 11 20 101 a) A cache hit occurs and 10 is read. b) A cache hit occurs and 5 is read. c) A cache miss occurs. d) A cache hit occurs and 20 is read.

c) A cache miss occurs.

Indicate the category for the instruction. Jump to instruction 90 a) Data transfer b) ALU c) Branch

c) Branch

The instruction, Load $t5 with DM[5150], falls into which instruction category? a) branch b) arithmetic logic unit c) data transfer d) data memory

c) data transfer

Finish translating this assembly instruction to a machine instruction: lw $t6, 0($t2) ___a____ __b__ __c__ 0000000000000000 1) a 2) b 3) c

1) 100011 (lw's opcode of 100011 is unique to lw, letting the hardware know this is a load word instruction.) 2) 01010 (In an lw machine instruction, the second field is the base address register, in this case $t2, whose encoding is 01010.$t0's encoding is 01000, and subsequent t register encodings count up in binary: $t1 is 01001, $t2 is 01010, $t3 is 01011, etc.) 3) 01110 (In an lw machine instruction, the third field is the destination register, in this case $t6, whose encoding is 01110.)

Assume $ra holds 116. If the jr instruction below is located in instruction memory at address 200, what is the address of the instruction executed after jr $ra?

116

If the jal instruction below is located in instruction memory at address 200, what value is written to register $ra? jal DetSpeed

204

Assuming $t6 holds 5020, complete the load instruction to load register $t2 with data at memory location 5044 using $t6 as the base address. lw $t2, ______ ($t6)

24

Type the stack as: 1, 2, 3 Given stack: 34, 20 (top is 34)Type the stack after the following two push operations: Push 11 to stack Push 4 to stack

4, 11, 34, 20

Type the stack as: 1, 2, 3 Given stack: 5, 9, 1 (top is 5) What is $t1 after the following pop operation? Pop stack to $t1

5

Assuming $t6 holds 5032, what is the base address for: lw $t5, 10($t6)

5032

Assuming $t6 holds 5072, from what memory address is the value loaded for: lw $t5, 24($t6)

5096

Assuming $t6 holds 6044, what is the offset for: lw $t4, 52($t6)

52

Type the stack as: 1, 2, 3 Given stack: 7, 5 (top is 7).Type the stack after the following push operation: Push 8 to stack

8, 7, 5

Type the stack as: 1, 2, 3 Given stack: 2, 9, 5, 8, 1, 3 (top is 2). What is $t2 after the following pop operations? Pop stack to $t1 Pop stack to $t2

9

Type the stack as: 1, 2, 3 Given stack: 5, 9, 1 (top is 5) Type the stack after the following pop operation: Pop stack to $t1

9, 1

Assembler

A program that converts assembly instructions into machine instructions (0s and 1s). The assembler's three main tasks are: 1) Replacing pseudoinstructions with native instructions 2) Determining each label's memory address 3) Generating machine instructions for the assembly instructions

Subroutine

A sequence of instructions that performs a specific operation that can be called from anywhere within a program. A subroutine call causes the subroutine's statements to execute.

Program stack

A stack used by a program to store data for subroutines

The CPU contains a register file and what other component?

ALU

Add immediate (addi)

Adds a register's value and an immediate value. An immediate is a value specified within an instruction.

Offset

An amount added to a base address to form a final address. In MIPS, the offset is a 16-bit number so can range from -32,768 to 32,767.

Pseudoinstruction

An assembly instruction that must be replaced by one or more native instructions before being executed

Executable file

Contains the 0's and 1's of a program's machine instructions and can be loaded into an instruction memory and then executed (run).

Opcode ("operation code")

Encode a machine instruction's operations like load word, store word, or add.

Operand

Indicate what register, address, or literal values are involved in an instruction

Stack overflow

Occurs when the number of values pushed to the stack exceeds the size allocated for the stack. Ex: Pushing 1005 values to the MIPSzy results in a stack overflow, as the stack size is limited to 1000 entries

Endianness

Refers to whether bytes in a word are ordered starting with the most-significant byte first (big-endian) or the least-significant byte first (little-endian).

Jump-and-link (jal)

Stores the address of the next instruction in register $ra, and then jumps to the instruction at the specified location.

$ra register (or return address register)

Stores the instruction address to which a subroutine returns after executing. The jump register (jr) instruction jumps to the instruction at the address held in a register.

Stack pointer ($sp) register

Used to hold the address of the top of the program stack

Instruction j Label is at address 001110..0100. Given an immediate field of 0..1010 (26 bits), what address will the CPU construct? a) 001100..101000 b) 001110..001010 c) 001100..001010 d) 001110..101000

a) 001100..101000

Assume the program stack is used for all subroutine arguments and return values. What is the stack frame size for a subroutine with one argument and no return values? a) 1 b) 2

a) 1

For an slt instruction, the first 6 bits are 000000, and the last 6 bits are _____ . a) 101010 b) 000000

a) 101010

In binary addresses below, the .. means enough 0's to form the indicated number of bits. For instruction beq $t0, $t1, Label, the beq instruction's address is 40, and Label's address is 60. What is the offset in decimal, before any adjustments for filling the 16-bit immediate field? a) 16 b) 20 c) 24

a) 16 (If the beq instruction's address is 40, the next instruction's address is 40 + 4 or 44. Thus the offset is 60 - 44 or 16.)

If an item is NOT found in cache, a cache ____ occurs. a) hit b) miss c) fault

b) miss

Given the following data memory (DM) and register file contents, which instruction performs the operation DM[5300] = 5304? Data Memory Register File 5300 -- 30 $t3 -- 5300 5304 -- 40 $t4 -- 5304 5308 -- 50 $t5 -- 5308 a) sw $t3, 0($t5) b) sw $t4, 0($t3) c) sw $t3, 0($t4) d) sw $t4, 0($t5)

b) sw $t4, 0($t3)

Given the following data memory (DM) and register file contents, which instruction performs the operation DM[5308] = DM[5300] + DM[5304]? Data Memory Register File 5300 -- 10 $t3 -- 5300 5304 -- 20 $t4 -- 5304 5308 -- 30 $t5 -- 5308 a) add $t5, $t3, $t4 sw $t5, 0($t5) b) add $t0, $t3, $t4 sw $t0, 0($t5) c) sw $t0, 0($t3) sw $t1, 0($t4) add $t2, $t0, $t1 lw $t2, 0($t5) d) lw $t0, 0($t3) lw $t1, 0($t4) add $t2, $t0, $t1 sw $t2, 0($t5)

d) lw $t0, 0($t3) lw $t1, 0($t4) add $t2, $t0, $t1 sw $t2, 0($t5)

Given the following data memory (DM) and register file contents, which instruction sequence performs the operation DM[5308] = DM[5300]? Data Memory Register File 5300 -- 5308 $t3 -- 5300 5304 -- 5304 $t4 -- 5304 5308 -- 5300 $t5 -- 5308 a) lw $t0, 0($t5) sw $t0, 0($t3) b) sw $t3, 0($t5) c) lw $t0, 0($t3) sw $t0, 0($t5) d) sw $t5, 0($t3)

c) lw $t0, 0($t3) sw $t0, 0($t5)

Given the following data memory (DM) and assuming $t0 holds 5304, $t1 holds 5308, which instruction sequence performs the operation DM[5308] = DM[5300]? Data Memory 5300 -- 10 5304 -- 20 5308 -- 30 a) lw $t1, 4($t0) sw $t1, -4($t0) b) lw $t0, -4($t1) sw $t0, 4($t1) c) lw $t1, -4($t0) sw $t1, 4($t0) d) lw $t0, 4($t1) sw $t0, 4($t1)

c) lw $t1, -4($t0) sw $t1, 4($t0)

Assume the program stack is used for all subroutine arguments and return values. For a subroutine with 2 arguments and a return value, which instruction loads the first argument to $t1. a) lw $t1, 0($sp) b) lw $t1, 4($sp) c) lw $t1, 8($sp)

c) lw $t1, 8($sp)

Assuming $t3 holds 5132, which store instruction stores the value of register $t2 to data at memory location 5144 using $t3 as the base address? a) sw $t2, 0($t3) b) sw $t2, $t3(12) c) sw $t2, 12($t3)

c) sw $t2, 12($t3)

Assume the program stack is used for all subroutine arguments and return values. For a subroutine with 1 argument and a return value, which instruction stores $t4 to the stack entry allocated for the return value. a) sw $t4, 8($sp) b) sw $t4, 4($sp) c) sw, $t4, 0($sp)

c) sw, $t4, 0($sp)

Given stack: 7, 5, 3, 1 (top is 7). What is $t0 after the following push and pop operations? Push 9 to stack Pop stack to $t0 Pop stack to $t0 Push 11 to stack a) 5 b) 9 c) 11 d) 7

d) 7

Consider a system with a memory hierarchy of a drive, memory, L2 cache, and L1 cache. When a program is run, where does the system look first? a) L2 cache b) Drive c) Memory d) L1 cache

d) L1 cache

Given the instruction sequence below, which instruction executes after the jal instruction? 20 -- sw $t0, 0($t2) 24 -- addi $t0, $t0, 5 28 -- jal CalcEq 32 -- sw $t0, 0($t2) ... CalcEq: 80 -- add $t1, $t0, $t0 84 -- addi $t1, $t1, 5 88 jr $ra a) sw $t0, 0($t1) b) addi $t1, $t1, 5 c) jal CalcEq d) add $t1, $t0, $t0

d) add $t1, $t0, $t0

Write a jump and link instruction to call a subroutine named CalcTip

jal CalcTrip

Using the $ra register, write an instruction to return from a subroutine named CalcTip.

jr $ra

Assuming $t5 holds 6000, write a load instruction that loads register $t3 with data at memory location 5960, using $t5 as the base address.

lw $t3, -40($t5)

Complete the assembly to pop a value from the top of the stack to $t4. __________________ addi $sp, $sp, 4

lw $t4, 0($sp)

Assuming $t5 holds 5000, write a load instruction that loads register $t4 with data at memory location 5048, using $t5 as the base address.

lw $t4, 48($t5)